The forward trace looks clean. Width is right. Length match is inside the table. Then the edge rings, the pair fails EMI, or a USB cable only works when you hold the shell. Nobody routed the signal wrong. They never designed the other half of the loop.
A FR4 PCB return path is not the ground symbol on the schematic. It is the copper the return current actually uses while the edge is in flight. Miss that copper and the geometry you calculated is only half a line.
Return Current Follows the Field, Not the Net Name
DC current takes whatever copper is cheapest. A ground via three inches away is fine for a 100 mA rail. Fast edges are not DC. The return sits under the trace because that is the lowest loop inductance. Adjacent plane. The far-side pour on 1.6 mm two-layer is a different loop.
Current leaves the driver on the signal copper and comes back on the nearest continuous reference that can support the same dI/dt. Ground, if it is there. A quiet power plane, if the stack put it next to the route and you stitched it. Air, if you deleted the copper. The schematic still says GND. The current does not read it.
The Shortest Return Is Under the Trace, Not Across the Board
Layout tools highlight the signal. They do not highlight the image current. So the "shortest path" people protect is the forward route. The return gets whatever copper is left after pours, slots, and via antipads.
On four-layer FR4 with thin prepreg to L2, that image current is a few tenths of a millimeter away. Keep L2 solid and the loop stays small. Same net over L4 through a 1.2 mm core and the loop is the stack height. Z0 moves. Radiation goes up. Different PCB signal return path.
If the plane is intact, the return is already the shortest AC path. You do not draw it. You stop cutting it. A gap and the current runs the pour edge to the nearest stitch via, cap, or connector shell. That detour is shared with every other net on the same edge. Crosstalk L1 geometry cannot fix.
A Plane Split Turns One Return Into a Slot Antenna
The split is usually intentional. Analog ground on one side, digital on the other. Two power domains sharing a layer. A copper-free strip so a connector cutout or a shield can sit down. All legal in CAM. All a wall if a fast net crosses them.
The return hits the gap and leaves the trace. It runs the slot. Loop area is slot length times stack height, not the spacing in the calculator. A 50 Ω or 90 Ω note on the drawing does not survive that segment.
Differential does not save you. Odd-mode current still wants a local plane return. Both members over the split: common-mode loop. One member only: two single-ended lines for that inch. Mode conversion looks like a shelf in the edge or a cable that radiates.
A stitch capacitor across the split only helps if it sits at the crossing. A 100 nF on the far side of the IC is a capacitor. It is not the return for a 200 ps edge three centimeters away.
A Layer Change Without a Return Via Is a Designed Discontinuity
Signal via from L1 to L3. Return still on L2 until it finds a ground via. That hop is inductance you did not put in the constraint manager. One ground via at the IC pin does not close a via three centimeters down the route.
Four-layer FR4, weekly. Channel is tight. Ground vias "later." Later is 4–5 mm off the pair because the escape filled first. At USB3 / HDMI / PCIe edges, a few millimeters is a stub in the return, not nearby.
Two ground vias flanking the pair at the hop is the minimum that closes the loop. One via shared by two pairs is common impedance. Antipads on the reference layer that merge along the escape are a split you miss at 50 % zoom.
Jumping from ground to a power plane is the same hole with extra parts. Vias plus capacitors at the transition. Not the PDN cap under the SoC. An islanded pour full of thermal reliefs is not a reference. Leave the signal on the ground-referenced layer.
Return Path Errors That Survive DFM and Fail the Interface
CAM does not flag a missing return. Fabrication will etch the width. Assembly will solder the PHY. The failure is electrical, later, on a cable or a chamber.
The list that keeps showing up in layout review is short and ugly.
Route the pair first, pour ground last, L2 is a maze of necks under the channel. Split analog and digital ground under a connector that carries both a sensor and USB. Use the outline or a mounting hole as the only bridge across a slot. Reference a clock to a power island that dies at the ferrite. Length-match two members that do not share a plane for the whole run.
Connector shell not stitched to the plane under the pairs — the cable is the rest of the return. Hold the metal and the error rate changes. That is the diagnostic. Through-hole connectors on two-layer FR4 punch slots in the only plane. The pairs cross them because there is nowhere else.
Via fences that look dense and are all signal plus one ground. Or grounds clustered at the driver while the receiver hops layers alone. Return current does not remember the first via. It needs one at this discontinuity.
What actually breaks
Signal integrity first: a reflection from the extra loop inductance, mode conversion on a pair, an eye that closes after a few inches of "correct" width. Then EMI. The slot plus the cable is an antenna. ESD and surge follow the same copper you left open. None of that is a fab yield issue. The board is buildable. The interface is not.
Design the Return Before You Commit the Route
Place the PHY and the connector so the interface stays on one layer over one solid plane as long as the budget allows. Every layer hop is a return via you buy. Every plane neck is a slot you route around or stitch at the crossing.
Do not split grounds under a fast edge. If analog isolation is required, put the split where USB, HDMI, PCIe, DDR, and clocks do not cross — stitch once, off that path. A ferrite in series with a pair return is worse than no split.
Ground vias in the same cluster as the signal vias. Both sides of a pair. Antipads on the reference layer stay separate. If L2 under a BGA is already lace, that pair does not belong on L1 over the lace. Move it or add a plane.
Two-layer 1.6 mm FR4 cannot give a close return. Far copper is too far. Every through-hole is a hole in the only plane. Interfaces that need a defined return live on four layers with thin dielectric to adjacent ground. Width changes on the thick stack do not invent that path.
Length-match after the return is frozen. Matching two traces that do not share a plane equalizes two bad loops. The TDR coupon sits on intact stack. Your pair does not.
Treat the FR4 PCB return path as layout, not as a net label. Solid adjacent copper. No slot under the edge. A return via at every layer change. Stitch at the crossing, not at the IC. The signal integrity problem on these boards is rarely the laminate. It is the loop the placement opened and the route never closed.
