Via-in-pad on FR4 looks clean on the layout screen. It shortens the path, frees routing channels, and gives a thermal pad a direct heat sink. Then the first assembled boards come back with starved joints or voids under the package. The via itself is not the problem. The open barrel is.
Most FR4 PCB via in pad decisions start the same way: the designer needs the pad real estate and does not want a dogbone. On standard FR4 that choice immediately triggers a process step most fabricators treat as an extra. If the via is left open, solder wicks down the barrel during reflow. The joint volume drops. Reliability follows.
Why the Via Ends Up Inside the Pad on FR4 Layouts
Density is the usual driver. Under a 0.4 mm or 0.5 mm pitch BGA the dogbone eats the only escape route left. Thermal pads on QFNs and power MOSFETs are the other common case. A solid copper connection straight through the pad beats a thermal via array outside the pad by a measurable margin in junction-to-board resistance.
Signal integrity sometimes enters the discussion for high-speed nets. The via stub is shorter when the via sits in the pad rather than beside it. On FR4 that advantage is real but secondary. Most via-in-pad calls are still mechanical or thermal, not impedance-driven.
The layout choice feels low-risk because the pad looks continuous in the CAD view. Fabrication reality is different. An open plated through-hole under a solderable surface is an open pipe for molten solder.
How Solder Moves When the Via Is Left Open
During reflow the solder paste melts and surface tension pulls it toward the cleanest copper surface. The plated via wall is that surface. Capillary action draws a portion of the solder volume down the barrel. On thin FR4 the travel distance is short; on thicker boards the volume loss is larger.
The joint that remains on the pad surface is under-volumed. X-ray shows voids or incomplete fillets. In extreme cases the component lifts slightly on one side because one pad has less solder than its neighbor. Thermal cycling later opens the starved joint first.
Paste volume calculation assumes a solid pad. Once the via is present that assumption is false unless the hole is filled and capped.
Resin Fill and Cap Requirements That Actually Get Enforced
Most FR4 shops treat via-in-pad as a filled-and-capped process. Non-conductive epoxy or resin is forced into the barrel, cured, then planarized. A copper cap is plated over the top so the pad surface is continuous again. Conductive fill is available but less common on standard FR4 because of cost and process control.
Fill percentage matters. Shops typically target 70–100 % fill. Anything below roughly 70 % still leaves a cavity that can trap air or accept solder. After planarization the surface should be flat enough that the subsequent copper plate produces a pad with no more than 25–50 µm of residual dimple or protrusion. Larger topography shows up in solder-paste printing as volume variation.
Aspect ratio limits apply. A 0.3 mm drill in 1.6 mm FR4 is manageable. Push the same drill into 2.4 mm or thicker material and complete fill becomes harder. Some fabricators will refuse the combination or require laser-drilled microvias instead.
IPC-4761 Type VII (filled and capped) is the usual call-out. Type III (plugged) is sometimes accepted for non-critical pads but leaves the risk of incomplete seal. Specify the type on the fabrication drawing; do not rely on a generic "via fill" note.
Assembly Risks That Appear After the First Reflow
Even with proper fill, surface finish and pad geometry still matter. ENIG or OSP over a capped via behaves normally. HASL can leave an uneven surface that changes paste release. The more critical risk is incomplete planarization. A residual depression under the paste stencil deposits less solder than the surrounding pads. The joint looks acceptable on visual inspection yet fails thermal shock earlier than neighboring joints.
On power pads the thermal benefit is real only if the fill material itself has acceptable thermal conductivity. Non-conductive resin is a thermal bottleneck compared with solid copper. Designers sometimes add a small array of filled vias under a large thermal pad to recover some of the lost path. That works, but each via still carries the process cost.
Long-term reliability tracks the quality of the fill. Micro-voids at the resin-to-copper interface can expand under repeated thermal cycling and eventually crack the copper cap. The failure is rarely catastrophic on first power-up; it shows up months later in the field.
When Via-in-Pad on FR4 Is the Right Call
Use it when the alternative is worse. Fine-pitch BGAs where dogbones simply do not fit. Thermal pads that must sink heat into an internal plane with minimal thermal resistance. High-current pads where every milliohm of path resistance counts.
Avoid it on cost-sensitive boards that can accept a conventional dogbone or staggered via. The process adder for fill and cap is real; on high-volume FR4 it can exceed the cost of a slightly larger package or an extra routing layer. Also avoid it when the board thickness and drill diameter push the aspect ratio past the fabricator's reliable fill window.
If the design is already moving toward HDI, laser microvias with copper fill are often cleaner than mechanical vias filled with resin. The decision is then no longer about FR4 via-in-pad process capability; it is about stack-up cost.
Practical Layout Rules That Keep the Process Stable
Call out the fill type and minimum fill percentage on the fabrication notes. Specify the maximum allowable surface topography after planarization. Keep the via diameter inside the pad consistent across the board so the fill process window stays the same. Do not mix open vias and filled vias under the same component package; the solder volume difference will show up as tilt or voids.
For thermal pads, calculate the expected heat path with the resin conductivity in mind rather than assuming solid copper. Add extra filled vias if the thermal budget is tight. On signal pads, verify that the finished copper thickness after capping still meets the impedance or current requirement.
The cleanest FR4 PCB via in pad designs treat the filled via as a controlled process feature, not as a free layout convenience. When the process is specified and the fabricator's capability is confirmed, the density and thermal gains are real. When it is left as an afterthought, the first reflow panel usually reveals the gap.
