Anyone who has built a high-speed board knows that signal-integrity problems are tied to vias more often than not. Much attention goes to trace impedance matching, while a quieter problem is ignored: via parasitic inductance. In measurement, an ordinary 1.0 mm via can present 1-2 nH. Above 5 GHz, that inductance is enough to close an eye and wipe out timing margin.
This article walks through where via parasitic inductance comes from and the methods used to reduce it. The practices come from production projects that already paid for the mistakes.
1. What the Signal Actually Sees Inside a Via
To fix the problem, start with the source. Via parasitic inductance comes from an abrupt change in the current path. The signal leaves a surface trace, enters the via, travels vertically along the barrel through the full board thickness, then exits into another trace. The geometry changes sharply: from a planar microstrip into a cylindrical conductor and back to a planar trace.
That path change has two effects.
The first is inductance. As current flows through the via, magnetic field lines close around the barrel. The area of that loop sets the inductance. A longer via (a thicker board) and a smaller drill increase the loop area and the parasitic inductance. A rough rule is that each millimeter of via length contributes about 0.5-1 nH.
The second is an impedance discontinuity. Via impedance is usually 40-60 Ω, which differs clearly from a 50 Ω single-ended trace or a 100 Ω differential pair. The discontinuity produces reflection. The reflection rides on the signal, causes ringing and overshoot, and in severe cases produces bit errors.
One point is easy to mix up: parasitic capacitance and parasitic inductance exist in the via at the same time. Parasitic capacitance mainly slows the rising edge and matters more at lower frequency. Parasitic inductance mainly affects return-path integrity and matters more at high frequency. In high-speed design, above 2 GHz, parasitic inductance does more damage than parasitic capacitance.
2. What Excess Parasitic Inductance Does: Three Typical Failures
1. The high-speed interface eye collapses
On PCIe, USB 3.0, and DDR4, the simulated eye can look open, then the built board shows insufficient eye height and excess jitter. The trail often ends at the via. Driven by a fast edge-rise time may be only tens of picoseconds-the inductive reactance XL = 2πfL can reach tens of ohms at 5 GHz and break the impedance-matching condition. The signal reflects back and forth at the via. That is where the jitter and inter-symbol interference come from.
2. Power integrity degrades and ripple exceeds the limit
Power vias have parasitic inductance as well. A chip power pin reaches an inner power plane through a via, and that inductance adds to the total impedance of the PDN (power delivery network). When the chip draws current suddenly-for example a CPU jumping from idle to full load-di/dt is large. The induced voltage V = L · di/dt on the via inductance can reach hundreds of millivolts, add to the supply ripple, and push the rail out of spec or disturb function.
3. EMC testing fails without an obvious SI fault
Sometimes signal integrity still looks acceptable and radiated emissions fail. The cause can be the via return path. When a signal via changes layers, the reference plane changes with it. If no return ground via is placed nearby, return current must travel a long way to find the new reference and forms a large current loop. That loop area is a radiating antenna: higher frequency and larger current produce stronger radiation. At the root, via parasitic inductance is still at work.
3. Why the Via Inductance Stays High: Root Causes and a Common Misread
Once the symptoms are clear, look at the causes. High via inductance is rarely one mistake. It is the sum of several steps.
First cause: board thickness was chosen without the via parameters. In many projects the mechanical engineer sets thickness first, such as a standard 1.6 mm board, and layout then drills ordinary vias in that stackup. 1.6 mm of thickness means 1.6 mm of via path. The rule of thumb then gives 1-1.6 nH. Where thickness allows, a thinner laminate or back-drilling to remove the via stub can cut the effective inductive length.
Second cause: no return ground via next to the high-speed signal via. This is the most common basic error. When the signal via changes layers, the reference switches from GND1 to GND2. Without a return ground via within 0.5 mm of the signal via, return current can only find the new plane through a distant capacitor or connector, and loop area jumps. In measurement, a signal via without a return ground via can show 50-100% higher equivalent inductance than one with a return via.
Third cause: via size was chosen casually. Some projects use one via size everywhere to save effort, such as a 0.3 mm drill and a 0.6 mm pad. That via is fine on low-speed nets. On signals above 5 GHz, the small drill narrows the current cross-section and raises inductance. The sound practice is a separate via rule for high-speed signals: a somewhat larger drill and a somewhat smaller pad, to reduce parasitics.
One misconception needs correction: more vias are not automatically better, even though paralleling vias can lower total inductance the way paralleled inductors do. If the vias sit too close, their magnetic fields couple and the parallel benefit shrinks. Add vias only as cost allows, and keep enough spacing. Hole pitch greater than twice the drill diameter is suggested.
4. Practical Ways to Cut Via Parasitic Inductance
With the causes known, the next step is the fix. The methods below run from easier to harder and can be combined.
1. Optimize via geometry
The most direct step, within fabricator limits, is a larger drill and a smaller pad. Raising the drill from 0.3 mm to 0.4 mm can cut parasitic inductance by about 15-20%. Shrinking the pad from 0.65 mm to 0.55 mm reduces parasitic capacitance between the via and the reference plane and indirectly eases the impedance discontinuity. Neither change is difficult for the board shop. The requirement is a separate via rule for high-speed signals in the design constraints, not the same via used on ordinary nets.
2. Always add a return ground via
The rule is simple and still skipped on real projects. When a high-speed signal via changes layers, place at least one ground via 0.3-0.5 mm from the signal hole, tied to every reference ground layer involved in that layer change. For a differential pair, place one ground via on each side to keep the return path symmetric. The ground-via drill can match the signal via or be slightly larger. Distance is the key: each extra 0.2 mm of spacing raises loop inductance by about 5-8%.
3. Back-drill the stub
On boards with more layers (eight or more), a signal via is often used between only one pair of layers, yet the hole runs through the full thickness. The unused length is the stub. A stub behaves as an open transmission line and can resonate at a particular frequency, showing up as a sharp impedance swing. Back-drilling removes the unused stub from the back of the board and shortens the electrical length of the via. After back-drill, insertion loss in the 5-10 GHz band can improve by 2-4 dB. Back-drill raises fabricator cost. For interfaces above 10 Gbps, that cost is worth paying.
4. Limit the number of layer changes
Each extra layer change adds a pair of vias, another impedance discontinuity, and more parasitic inductance. During floorplanning, assign high-speed routing layers first and reduce layer changes. When a change is unavoidable, prefer adjacent signal layers, such as L3 to L4, so the via is shortest and the inductance is lowest. Jumping from L1 straight to L8 is a last choice in high-speed work unless the mechanics leave no other path.
5. Close with simulation
The methods above are experience-based. For a critical high-speed interface such as PCIe Gen4/Gen5 or 112G PAM4, experience is not enough. Run 3D electromagnetic simulation of the via. Tools such as HFSS, CST, or SIwave can build an accurate via model, extract S-parameters, and check whether return loss (S11) and insertion loss (S21) stay inside the channel budget. Simulation finds what the rule of thumb misses, including coupling to nearby copper and the shape of the reference-plane opening. The simulation cost is modest and can save at least one prototype cycle.
Via parasitic inductance is not finished by one trick. Stackup planning, via rules, return-path design, process choice, and simulation all have to hold. Saving a step in each place becomes a production problem. Doing one extra step in each place lifts signal quality by a grade.
Hardware design is not only schematic skill. It is control of each physical detail. A via looks like a small hole in the board. To a high-speed signal it is a transmission structure that has to be designed. When the via is designed well, high-speed interface margin rises with it.
