This article investigates solder bridging between vias and test pads during palletized wave soldering, starting from defect observation and fishbone analysis through a structured design of experiments (DOE) and validation runs. The work covers both PCB layout factors and process parameters, and concludes with actionable design and process recommendations to suppress bridging while maintaining manufacturing efficiency.
Problem Analysis
Overview
On a given product line, via and test-pad solder bridging accounted for 2–3% of total defects. The existing design guideline for wave soldering specified a minimum via spacing based on conventional wave soldering trials. However, solder-flow behavior differs significantly when solder pallets (fixtures) are used during wave soldering, and via-to-via bridging became a prominent defect mode under palletized conditions.
Typical through-hole solder bridging observed on single boards is shown below.
Figure 1 | Typical solder bridge between adjacent vias/test pads on a single board
From the observed defects, two classes of causes were suspected: (1) insufficient spacing between plated through holes (PTHs) or test pads; and (2) suboptimal wave solder process parameters. Controlled trials were required to verify and quantify the impact of each factor.
Root Cause Analysis of Solder Bridging
Solder bridging is a common defect in palletized wave soldering, particularly when adjacent through-hole vias or test pads are closely spaced. To identify the primary causes and develop effective countermeasures, this study evaluated both wave soldering process parameters and PCB layout characteristics.
The initial fishbone analysis identified three major categories of potential causes: wave soldering parameters, PCB hole spacing, and pallet opening design.
Process-related factors included flux deposition, preheat temperature, solder-wave temperature, wave height, and conveyor speed. Insufficient flux can reduce wetting and increase bridging risk, while excessive flux may contribute to residue and process instability. Improper preheating can compromise flux activation or cause excessive solvent evaporation. Similarly, a solder-wave temperature that is too low can impair wetting and drainage, whereas excessive wave height may increase solder carryover and tailing. Conveyor speeds that are too high can also reduce the time available for excess solder to drain from the board.
PCB layout and pallet design are equally important. When the edge-to-edge spacing between adjacent vias or test pads is too small, molten solder can remain connected across neighboring features. Pallet openings that are too small or poorly shaped may restrict solder circulation and drainage, increasing the likelihood of solder accumulation and bridging.
How Solder Bridges Form During Wave Soldering
The formation of solder bridges is governed by the interaction of surface tension, solder wetting, meniscus formation, drainage dynamics, and flux activity.
As the PCB passes through the solder wave, molten solder wets exposed copper surfaces and forms menisci around through-hole features. When adjacent solderable surfaces are too close together, or when excess solder remains between them, these menisci may merge into a continuous solder connection. After the board exits the wave, insufficient drainage time or restricted solder flow can prevent the connection from breaking cleanly.
Flux activity affects wetting behavior, while preheat conditions influence flux activation and solvent evaporation. Wave temperature and height determine solder behavior and the amount of solder carried onto the PCB, and conveyor speed affects both wave contact time and post-wave drainage.
Consequently, solder bridging should not be attributed to PCB spacing alone. Reliable defect reduction requires a coordinated evaluation of layout geometry, flux deposition, wave conditions, and pallet design.
Experimental Design for Wave Soldering Optimization
Selection of Process Factors
A design of experiments (DOE) approach was used to evaluate the effects of flux deposition and conveyor speed on solder bridging. Five process parameters were initially considered: flux deposition amount, preheat temperature, solder-wave temperature, wave height, and conveyor speed.
However, not all five parameters were varied independently. For palletized wave soldering, component-side preheat is influenced by multiple heating sources, including hot air, high-temperature lamps, and infrared heaters. Because these thermal conditions are also related to conveyor speed, independently varying preheat would have increased the complexity of the experiment.
The component-side preheat was therefore maintained at a target of 85 °C, with conveyor speed used to manage the thermal exposure within the established process window. The solder-wave temperature was fixed at 248 °C, a typical production setting for leaded products. Wave height was also held constant at a practical production setting corresponding to approximately half the PCB thickness.
With these conditions controlled, the DOE focused on two factors: flux deposition and conveyor speed. Flux deposition was evaluated at gear settings 4, 5, and 6, while conveyor speed was tested at 0.9, 1.0, and 1.1 m/min.
The resulting full-factorial design comprised nine unique parameter combinations. With one replication, the planned experiment included 18 runs. Each executed run processed 10 boards, with the number of boards adjusted according to the specific experimental phase.
The original sampling plan also considered the requirement of NP > 5 and targeted a sample size exceeding 50,000. Because these criteria relate to defect-rate estimation and statistical confidence, they should be distinguished from the number of experimental runs and the number of boards processed per condition.
Measurement System Validation
Before conducting the experiments, the temperature measurement system was evaluated using a Gage R&R study.
Two thermocouples simultaneously measured the same test point during each pass through the soldering process. Twenty passes were recorded, producing 20 experimental units and 40 temperature readings. Since each pass was subject to its own equipment conditions and thermal history, the units could not be reproduced under identical conditions. The study therefore focused on measurement repeatability rather than a complete assessment of reproducibility.
The resulting Gage R&R value was 18.64%, below the commonly used 30% acceptance threshold. This indicated that the temperature logger and test board were suitable for the subsequent temperature measurements, although the limited study design should be considered when interpreting the measurement system's overall capability.
PCB Test Coupon and Layout Factors
A dedicated test coupon was designed to investigate the effects of PCB geometry on solder bridging. The primary factors were the edge-to-edge spacing between adjacent vias or test pads and the distance from each feature to the pallet edge.
Via-to-via spacing was varied from 0.2 to 0.7 mm in 0.1 mm increments. The distance to the pallet edge was evaluated at 0.5, 1, 2, and 3 mm. Secondary factors included hole diameters of 8, 10, and 12 mil, as well as the presence or absence of copper pour.
A full-factorial layout experiment was conducted across the two primary factors to isolate their effects under controlled soldering conditions. The pallet openings followed the company's established design guidelines for palletized wave soldering, helping to maintain consistency across test conditions.
Experimental Procedure and Process Settings
The experimental program used 180 boards containing through-hole components, five solder pallets, a designated wave soldering line, and a forming and insertion line. The trials were conducted during the planned experimental period with support from production operators, an equipment engineer, and R&D engineers.
Before the DOE runs, the actual flux deposition at each gear setting was measured to confirm the experimental factor levels. Gear 4 delivered 2.2013 mg/cm², gear 5 delivered 2.4876 mg/cm², and gear 6 delivered 3.000 mg/cm². These results were consistent with the nominal targets of 2.0, 2.5, and 3.0 mg/cm², respectively.
The wave soldering process used water-based flux with full-spray deposition rather than sensor-based deposition. The first wave was not used, and the second-wave pump setting was recorded as 530 turns. Because this pump setting was not considered a stable absolute measure of wave height, it was treated as an equipment setting rather than a directly transferable process specification.
The solder-wave temperature remained at 248 °C throughout the trials. The preheat configuration was held constant, with hot air set to 150 °C and the three lamp zones set to 450 °C, 430 °C, and 480 °C. Top heating power was set to 25% for Top 1 and 30% for Top 2.
Components were preformed and inserted before soldering, and the DOE runs were performed in randomized order to reduce the risk of systematic bias. Ten boards were processed for each run.
Results and Statistical Analysis
Effect of PCB Spacing on Solder Bridging
Across the layout experiment, 180 boards were inspected, covering 25,920 solder joints on the test coupon. A total of 1,100 solder bridges were recorded.
The results showed a clear relationship between via-to-via spacing and bridging probability. Spacings of 0.2 and 0.3 mm exhibited substantially higher bridging rates than the larger spacings evaluated in the experiment.
This finding indicates that edge-to-edge spacing between adjacent solderable features is a major design factor in palletized wave soldering. Increasing the spacing provides more room for molten solder to separate during drainage, reducing the likelihood that neighboring solder menisci remain connected.
By comparison, the distance between a via or test pad and the pallet edge was not a primary driver within the tested range. This does not mean pallet-edge distance is universally irrelevant; its effect may change with pallet opening geometry, wave behavior, or other process conditions.
The results therefore support prioritizing via-to-via spacing during PCB layout reviews, while retaining appropriate controls over pallet design and soldering conditions.
DOE Results: Flux Deposition and Conveyor Speed
The process DOE evaluated the effects of flux deposition, conveyor speed, and their interaction on solder-bridge counts. A general linear model was fitted using adjusted sums of squares.
Flux deposition was statistically significant in the two-factor model, with a p-value of 0.005. A separate single-factor ANOVA produced a p-value of 0.002, providing consistent evidence that flux deposition influenced the observed defect counts.
Conveyor speed was not statistically significant within the tested range. Its p-value was 0.893 in the two-factor model and 0.953 in the single-factor analysis. The interaction between flux deposition and conveyor speed was also not significant, with a p-value of 0.282.
These results suggest that adjusting flux deposition had a more measurable effect on bridging than changing conveyor speed between 0.9 and 1.1 m/min under the experimental conditions. However, the lack of statistical significance for conveyor speed should not be interpreted as proof that speed never affects solder bridging. Its influence may become more pronounced outside the tested range or under different thermal and drainage conditions.
Selection of Production Parameters
The DOE matrix plots showed that flux gear 5 produced the lowest solder-bridge counts among the three tested levels. This setting also provided a practical balance between defect reduction and flux residue control.
Although conveyor speed did not show a statistically significant effect on defect counts, the results at 1.0 m/min were more tightly distributed. Selecting this speed therefore provided a practical operating point for consistent production and easier process monitoring without sacrificing throughput.
No consistent pattern was observed in the interaction plots, which aligned with the non-significant interaction term in the statistical model.
Based on the combined statistical results and manufacturing considerations, flux gear 5 and a conveyor speed of 1.0 m/min were selected for the subsequent layout-spacing experiments.
Validation of the Selected Process Window
A validation run was performed using flux gear 5 and a conveyor speed of 1.0 m/min. The test involved 120 boards with a via/test-pad spacing of 0.4 mm.
The validation produced 27 solder bridges across 1,201,200 solder joints, based on 10,010 joints per board. This corresponds to a defect rate of approximately 22.48 defects per million opportunities (DPMO), or 22.48 ppm when expressed on a per-joint opportunity basis.
The result was below the project's target of 100 ppm, demonstrating that the selected process settings achieved the required performance under the validation conditions.
Conclusions and Recommendations
This study combined PCB layout experimentation with wave soldering DOE to investigate solder bridging in palletized wave soldering. The results identified via-to-via spacing as the dominant layout factor and flux deposition as a statistically significant process factor.
For PCB design, an edge-to-edge spacing greater than 0.4 mm is recommended as a starting design guideline for reducing bridging risk under comparable manufacturing conditions. The experiment showed substantially higher bridging probabilities at 0.2 and 0.3 mm. However, the exact minimum spacing should be confirmed against the PCB design, solderable feature geometry, pallet construction, and qualified production process. A spacing of 0.4 mm should not be interpreted as a universal guarantee against bridging.
For process control, flux gear 5, corresponding to a measured deposition of approximately 2.49 mg/cm², and a conveyor speed of 1.0 m/min are recommended as the preferred settings within the tested process window. The solder-wave temperature was maintained at 248 °C, while preheat and wave height were controlled at their established production settings.
The distance from the via or test pad to the pallet edge was not a dominant factor within the evaluated range. Nevertheless, pallet opening design and drainage behavior should remain part of the process qualification because changes in geometry can alter solder circulation and carryover.
In the specific case analyzed, a pad edge-to-edge spacing of 0.59 mm is a reasonable design choice. The observed bridging issue should be assessed through both layout and process controls rather than attributed to PCB geometry alone.
Overall, the study demonstrates that combining adequate PCB feature spacing with controlled flux deposition and a stable wave soldering process can substantially reduce solder bridging. The validation result of 22.48 ppm met the project's target of less than 100 ppm, providing quantitative support for the selected countermeasures.
For production implementation, these settings should be treated as a qualified process window rather than universal machine settings. Confirmation runs, ongoing defect monitoring, and periodic verification of flux deposition, preheat, wave conditions, and pallet integrity are recommended to sustain performance.
