PCB design is not stacking circuits. It is a system built from details. Asymmetric pad exits can tombstone a part. A signal that crosses a plane split can drive EMI out of limit.
The notes below cover layout details that commonly fail in practice.
High-Voltage and Low-Voltage Signals Must Be Hard-Partitioned
Switch-mode power PCBs often place high-voltage, high-energy circuits on the same board as low-voltage control. The power section, such as MOSFETs and power inductors, and the control signals, such as PWM and feedback, must be strictly partitioned. That keeps high-voltage noise from entering the control circuit, causing false operation or even damaging the board.
Figure 1 | Isolated layout of high-energy and low-energy signals
Place the Crystal Tight Against the Controller
A crystal oscillator has limited drive capability. In a high-speed digital system, placing it far from the main controller can cause:
- Signal attenuation
- Square-wave distortion
- Clock skew and system stalls
Place the crystal directly next to the chip. Keep the PCB traces short, straight, length-matched, and symmetric.
Figure 2 | Crystal routing close to the main controller
Reuse Modules for Repeated Circuit Blocks
On a control board with eight input channels and eight drive channels, the blocks repeat. Use the module-reuse function in the PCB tool to unify placement and keep routing symmetric. That saves time and reduces errors.
Figure 3 | Symmetric layout using module reuse
Place Parts So People Can Work on the Board
During debug, hands, probes, and a hot-air tool all need space.
- Do not put a large part next to a small part and block access.
- Leave room beside trimmers, adjustable capacitors, and jumpers.
- Do not let through-hole parts cross or overlap.
Figure 4 | Component placement that leaves room for debug
Put Decoupling Capacitors Against the Power Pins
When power enters a chip, voltage ripple and spike noise can appear. The decoupling capacitor absorbs that disturbance.
- Place the capacitor next to the IC power pin. Closer is better.
- Form the smallest power-capacitor-ground loop.
Figure 5 | Preferred decoupling-capacitor placement
Crossing a Split Breaks Signal Integrity
On a multilayer PCB, if a signal leaves one reference region and enters a different region, such as leaving a GND-referenced area for a voided area, the return path breaks. EMI rises and signal quality drops sharply.
High-speed traces in particular must not be routed across a split.
Figure 6, Figure 7 | Incorrect and correct treatment of a plane split
Asymmetric Pad Exits Cause Placement Shift
If pad exits leave on a diagonal, solder-mask shift can rotate or offset the part and degrade the joint.
Correction:
- Keep fan-out symmetric along the long axis.
- If short-axis symmetry can also be kept, offset is reduced further.
Figure 8, Figure 9 | Rotation caused by pad exits and the correction
Differential Routing: Length Matching Is Not Optional
A common mistake is to assume that equal spacing is enough for a differential pair. What actually governs synchronization is length.
- Route the pair together.
- Give length matching priority over identical spacing.
- Leave serpentine room to adjust length.
Figure 11 | Length-matching method for a differential pair
High-Frequency Traces Need Ground Guarding or Isolation
If clock, USB, LVDS, and other high-frequency signals are not isolated electromagnetically, they can:
- Crosstalk into adjacent traces
- Create EMI problems
Approach:
- Guard with ground. Enclose on three sides when possible.
- If space is insufficient, keep at least 3W spacing.
Figure 12 | Ground-guard and spacing practice for high-frequency signals
Vias Packed Too Tightly Fracture the Reference Plane
On a multilayer PCB, too many vias or a dense via row can cut the GND/VCC reference plane and cause:
- A longer signal return path
- An impedance discontinuity
- Scattered noise
Keep via spacing wide enough for a trace to pass, and avoid fracturing the ground plane.
Figure 13 | Plane fracture caused by packed vias
Gold Fingers Need a Full Solder-Mask Opening
Gold fingers are inserted and removed repeatedly. If solder mask is left on them, it can flake off over time and cause:
- Higher contact resistance
- Poor contact
Preferred practice:
- Add the opening region in the footprint.
- When drawing the solder-mask layer, keep the fingers fully open.
Figure 14 | Correct solder-mask opening on gold fingers
Keep the Footprint Symmetric to Avoid Tombstoning
Tombstoning is unbalanced force at the two ends. It is mainly caused by:
- Unequal pad area
- Inconsistent pad shape
Keep the pads fully symmetric in the footprint to keep the part from standing up during reflow.
Figure 15 | Tombstoning and pad design
Closing
A high-end schematic still fails if the details do not hold. Items that look unimportant are often the ones that break the board. PCB design is built from those small geometric and process details.
