After a product enters volume production, sample inspection keeps finding units whose MCU does not run at power-up. A reset starts the board. Replacing the crystal fixes that unit, then the same failure returns a few days later. The line keeps sending boards back, and yield will not rise.
The root cause is the crystal circuit: the wrong load capacitors, poor PCB routing, and a missing feedback resistor. Those small errors stack until oscillation margin is gone. A temperature change or a new crystal lot is then enough to keep the oscillator from starting. The circuit looks simple — one crystal and two capacitors — and that is why it is ignored, and why the failure is hard to isolate.
1. Why the Crystal Does Not Start
1.1 The oscillation conditions are not met
A crystal oscillator starts only when two conditions are met: loop gain greater than 1, and loop phase shift an integer multiple of 360 degrees. In other words, the amplifier must supply more gain than the crystal network dissipates, and the signal must return in phase after one trip around the loop.
Near its resonant frequency the crystal behaves as a high-Q LC network. Frequency selectivity is strong, and so is the demand on gain. If gain margin is thin, the oscillator may start at room temperature and then fail when temperature changes or when crystal parameters spread from part to part.
1.2 Insufficient negative resistance — the specification most often ignored
Negative resistance is the core measure of how hard the oscillator can drive the crystal. The amplifier inside the MCU is equivalent to a negative resistance in series with a reactance. Larger negative resistance means stronger drive.
The crystal has an equivalent series resistance (ESR). Negative resistance must be 3 to 5 times the ESR if the oscillator is to start reliably under all conditions. Many engineers never calculate negative resistance and pick capacitors from typical datasheet values. A crystal lot with higher ESR then fails. The symptom of weak negative resistance is intermittent startup — it works on some boards and not on others, with no obvious pattern.
2. Common Design Mistakes
2.1 Incorrect load-capacitance calculation
The crystal load capacitance CL relates to the external capacitors as:
CL = (C1 × C2) / (C1 + C2) + Cs
Cs is stray capacitance from the PCB and pins, typically 3 to 7 pF. Many engineers calculate only the series combination of C1 and C2 and omit Cs. Actual load capacitance then runs high and oscillation frequency runs low.
A more common error is choosing C1 and C2 unequal. Unequal values are allowed in principle, but a large mismatch makes the waveforms at the two crystal pins asymmetric and reduces startup margin.
Another trap: the crystal datasheet specifies 12.5 pF load capacitance. The design uses C1 = C2 = 18 pF and assumes 5 pF of stray capacitance. On the real PCB, stray capacitance may be 8 pF or even 10 pF, so actual CL exceeds 17 pF and sits far from 12.5 pF. Frequency error can then break MCU USB or Ethernet communication.
2.2 Missing or incorrect feedback resistor
A Pierce oscillator needs a feedback resistor across the crystal. That resistor biases the internal amplifier into the linear region. Without it, the amplifier can sit in saturation or cutoff and the oscillator will not start.
Some MCUs integrate this resistor; some do not. The datasheet states which is which, and it is often unread. An external feedback resistor is typically 1 MΩ to 10 MΩ. Too small a value raises power and lowers Q. Too large a value is easily disturbed by leakage in a humid environment.
2.3 Poor PCB layout
Crystal traces are among the most sensitive nets on the board, yet they are often treated as ordinary wiring. Typical errors include traces that are too long, routes that pass near noise sources, load capacitors placed far from the crystal pins, and a broken ground plane. All of those increase stray capacitance, couple in noise, and reduce oscillation margin.
Place the crystal as close as possible to the MCU pins. Keep the traces as short as possible. Put both load capacitors next to the crystal pins and return them to the same ground point. Do not run other signals under the crystal. A continuous ground plane under the circuit is preferred. These are basic placement rules, not advanced techniques. The difference between following them and ignoring them can be the difference between 99% yield and 100% yield.
2.4 Excessive drive level
A crystal has a maximum drive level, usually between 100 μW and 300 μW. If the circuit delivers more than that, the quartz blank vibrates too hard, ages faster, and can be damaged. The later symptom is growing frequency drift and, eventually, failure to start.
Excessive drive often comes from load capacitors that are too small. Smaller capacitors increase feedback and raise the voltage swing across the crystal. Reducing load capacitance to "correct" frequency can push drive level over the limit and cost more than it gains.
3. How to Verify Crystal-Circuit Reliability
3.1 Measure negative resistance
Insert a variable resistor in series with the crystal branch and increase it until the oscillator just fails to start. That resistance is the negative resistance. It should be at least 3 to 5 times the crystal ESR. A measured ratio of only 1 to 2 times means the margin is too small for volume production.
3.2 Hot and cold startup tests
Run startup tests across the product's operating temperature range. At each temperature, power the board at least 50 times. Startup at room temperature does not prove startup at low temperature. MCU gain changes with temperature, and crystal ESR rises. This test belongs in the pre-production plan. Finding the failure at a customer site is too late.
3.3 Verify more than one crystal lot
ESR can differ from lot to lot, especially after a supplier change. Before production, test at least two lots and confirm that negative-resistance margin still holds.
The crystal circuit is one of the most underestimated blocks in hardware design. Behind two capacitors and one crystal sit negative-resistance margin, load-capacitance accuracy, PCB parasitics, and drive-level limits. Startup failure is rarely one cause. It is several small errors stacked together: capacitance off by 2 pF, a trace 5 mm too long, a missing feedback resistor, stray capacitance higher than assumed. None of those is fatal alone. Together they consume the oscillation margin. One extra calculation in design prevents a batch of rework in production.
