During CAM preparation of an 8-layer order classified as HDI, our team identified three items that required customer confirmation before tool generation could proceed. The board is specified as Shengyi S1000-2M FR-4 with TG170, 1.6 mm finished thickness, 1 oz copper on outer and inner layers, immersion gold, and matte black solder mask. Impedance control is required, the hole size is listed as 0.15 mm, and the delivery format is customer self-panelization with no process edge. The engineering files, however, presented a conventional 8-layer stackup while also containing blind vias, and the 50 ohm impedance requirement lacked a corresponding trace width.
The main engineering questions centered on whether copper poured on the process edge for current balancing was acceptable, whether the missing trace width for the 50 ohm impedance could be resolved, and whether the supplied conventional lamination structure could be used when blind vias were present. These points directly affect plating uniformity, impedance artwork, and the lamination sequence.
HDI PCB Copper Pour for Plating Current Balance
Our CAM review noted that the order ( #HDI-20251209-0002 ) form indicates no process edge. In practice, a process edge is often retained for handling, tooling holes, and plating current distribution. Because the panelization is customer-supplied and no process edge is called out, plating current distribution across the panel becomes a concern, particularly with 1 oz copper and immersion gold.
To improve current balance during plating, our engineer added copper pour on the process-edge area and submitted the resulting layout for confirmation. The copper pour is intended to equalize current density so that the functional area receives more uniform copper thickness. Without such balancing, edge effects can produce thinner copper near the panel boundary and thicker copper toward the center, which in turn affects impedance, annular-ring integrity, and final surface-finish thickness.
Figure 1: Copper has been poured on the edge rails for current balancing, as shown.
Because the customer files did not include a process edge, the added copper constitutes a manufacturing adjustment rather than a design feature. Confirmation is required to ensure the pour does not interfere with the customer's intended panel outline, tooling, or any unstated keep-out zones. Once accepted, the copper can be retained in the working files; if rejected, an alternative balancing method would need to be evaluated.
50 Ohm Impedance Control: Missing Trace Width Specifications
The order indicates that impedance control is required and that no impedance report is requested. Examination of the files showed a 50 ohm requirement, yet no corresponding trace width was stated. We therefore asked the customer to clarify the intended line width for the 50 ohm geometry.
Impedance is determined by trace width, dielectric thickness, copper weight, and the dielectric constant of the Shengyi S1000-2M material. Without a specified width, the factory cannot generate the inner-layer or outer-layer artwork that will meet the target. In a conventional calculation the dielectric spacing to the nearest reference plane would be used to solve for width; however, the files did not supply either the width or a customer stackup drawing that would fix the dielectric distances. The absence of this information prevents both the impedance compensation and the final copper artwork from being released.
Figure 2: As shown in the diagram, the required 50-ohm impedance control does not specify a corresponding trace width.
Because the board is 1.6 mm thick with 1 oz copper, small changes in dielectric thickness produce measurable shifts in the width needed to hold 50 ohms. Customer confirmation of the desired width, or acceptance of a factory-calculated width based on a defined stackup, is therefore a prerequisite for proceeding. The lack of an impedance report means that once the width is agreed, verification will rest on the customer's acceptance of the calculated geometry rather than on a post-fabrication measurement report.
8-Layer HDI PCB Stack-Up Requirements for Blind Vias
The most significant process conflict identified in the files is the combination of a conventional 8-layer lamination structure with the presence of blind vias. The stackup supplied with the order is the standard single-lamination 8-layer construction. Blind vias, however, cannot be formed in a single lamination cycle; they require sequential build-up in which sub-composites are laminated, drilled (normally by laser), plated, and then laminated again.
Figure 3: The provided standard 8-layer stack-up is not compatible with the blind vias in this design
Our engineer noted that the board contains blind vias and therefore cannot be fabricated with the conventional press cycle shown in the customer stackup. A 3-order or multi-order HDI construction on an 8-layer board typically involves at least one or two sequential lamination steps so that the blind interconnects can be created at the appropriate layer pairs. Using a single-lamination stackup would leave the blind vias either undrilled or drilled through layers they are not intended to connect, producing open circuits or unintended shorts.
The order form classifies the board as HDI and lists a 0.15 mm hole size, which is consistent with microvia or small blind-via features, yet the supplied lamination drawing does not reflect the sequential process those features demand. Confirmation is required on whether the customer will accept a revised sequential stackup that accommodates the blind vias, or whether the blind features can be removed or converted to through vias. Until that decision is made, neither the drill files nor the lamination sequence can be finalized.
Figure 4,5: The stack-up has been adjusted to meet both the thickness and impedance requirements.
This stackup mismatch also interacts with the impedance question. A sequential HDI PCB stackup changes the dielectric thicknesses seen by the signal layers relative to a conventional 8-layer press. Any 50 ohm width calculated on the conventional stackup would no longer be valid once the lamination sequence is altered to support the blind vias. The two items therefore need to be resolved together.
HDI PCB Layer Order Verification Before Sequential Lamination
Supporting records indicate that the Gerber set did not include layer-order information. Our team reconstructed a layer sequence and requested confirmation. While that item sits outside the main query, it is relevant because a correct layer order is a prerequisite for defining which blind-via spans are possible and for assigning the proper dielectric thicknesses in any revised HDI stackup. An incorrect layer assignment would invalidate both the blind-via connectivity and the impedance geometry.
The absence of a layer-definition file is a common contributor to the type of stackup conflict seen here. Without an explicit build-up drawing, the CAM engineer must infer the intended sequential structure from the copper and drill layers alone. Customer confirmation of both the layer order and the revised stackup removes that ambiguity before any sequential lamination tooling is generated.
HDI PCB CAM Review: Key Manufacturing Issues and Customer Confirmation
The three items in the main engineering query are interdependent. The process-edge copper pour addresses plating uniformity on a panel that has no defined process edge. The missing 50 ohm trace width prevents impedance artwork from being generated. The conventional stackup cannot produce the blind vias that are present in the design. Resolving the stackup first is necessary because it fixes the dielectric thicknesses that will be used to calculate the impedance width; the copper-pour decision can then be finalized against the agreed panel outline.
None of these points can be closed by the factory alone. Each requires an explicit customer decision: acceptance of the balancing copper, provision or acceptance of a 50 ohm trace width, and agreement on a sequential lamination structure that supports the blind vias. Once those decisions are received, the working stackup, impedance compensation, drill programs, and panel copper can be locked and the job released for sequential build-up. Until then, the manufacturing risk is that a conventional press cycle would be applied to a design that contains features it cannot form, or that impedance artwork would be generated on dielectric thicknesses that will not exist in the final board.
The case illustrates a frequent CAM situation with HDI orders: the combination of an incomplete stackup drawing, missing impedance geometry data, and the absence of a process edge forces a focused set of confirmation questions rather than a single global change. Addressing each item against the actual process constraints of sequential lamination, plating uniformity, and impedance control keeps the design intent intact while bringing the board inside the manufacturing window.
