A 6-layer HDI board with TG170 material, 1.6 mm finished thickness, ENIG finish, and matte black solder mask arrived for CAM review. The design showed 1 oz copper on inner and outer layers, minimum hole size of 0.3 mm, and hole density reaching 39,000 per square meter. Customer self-panelization was specified with no process edge and V-cut separation. From a DFM perspective, the combination of high hole density and unclear hole attributes immediately raised concerns about plating integrity and long-term via reliability. Production could not proceed until these points were clarified because the risk of open circuits or weak plating was real.
DFM review mattered here because the files contained multiple ambiguities that standard design checks had not flagged. Without engineering confirmation, the board could enter fabrication with plating decisions that did not match the designer's intent. That mismatch is a common source of yield loss on dense via boards.
Why This 6-Layer Design Required Thorough DFM Review
The project complexity came from three factors visible in the order and Gerbers. First, hole density of 39,000 per square meter on a 216 mm by 280 mm panel leaves little margin for drill wander or plating variation. Second, HDI stage 1 was listed even though blind and buried vias were marked as none, which still implies tighter registration tolerances. Third, the customer requested production factory code addition while marking production confirmation as no. These indicators told the CAM team that design intent needed explicit confirmation before any toolpaths or plating cycles were locked.
Risk indicators also appeared in the fabrication notes and layer data. Trace width and spacing were given as 4, solder mask was matte black on both sides, and vias were specified for tenting. None of these alone is problematic, but together they amplify the consequences of any hole attribute error. A single misclassified via in a high-density PCB region can create an open that only appears after thermal cycling or assembly.
The Most Significant Manufacturability Risks Identified
CAM review focused on the five engineering questions raised from the Gerbers. Three of them carried genuine yield or reliability impact; the remaining two were procedural. The primary concern was manufacturing stability around hole plating and panel handling.
Ambiguous Hole Plating Attribute on Same-Size Drills and Pads
Our CAM engineer noticed that several internal board drills matched the diameter of their associated circuit pads exactly. The hole attribute was listed as copper hole, yet no copper skin connected the pad to surrounding traces or planes. Under standard CAM interpretation, a plated hole requires annular ring and copper connection to support reliable plating adhesion and current path. Because those features were absent, the team defaulted to non-copper hole (NPTH) processing. This decision needed customer confirmation because the original attribute contradicted the geometry.
Figure 1: This holes would be made as NON copper
Missing Positioning Holes on the Specified Process Edge
The order listed process edge as none (0 mm) and shipping type as customer self-panel, yet the Gerbers showed a process edge region without any positioning holes. Further verification revealed that the edge geometry existed in the outline layer but contained no fiducials or tooling holes. Without them, registration between layers and between the panel and downstream assembly fixtures becomes dependent solely on the board outline, which is less precise on a V-cut panel.
Figure 2: There is no tooling holes in the design
Overlapping Silkscreen Characters
Multiple character strings in the top and bottom silkscreen layers overlapped to the point that individual glyphs could not be distinguished. The fabrication notes called for white silkscreen and addition of the production factory code. Overlap does not stop fabrication, but it creates downstream identification risk and can mask the added factory code once the board is populated.
Figure 3: The silkscreen overlaps in the design and are indistinguishable
| EQ Item | Severity | Primary Concern | Immediate Action |
|---|---|---|---|
| Same-size drill and pad, no copper connection | High | Plating adhesion and via continuity | Treat as NPTH pending confirmation |
| Process edge without positioning holes | Medium | Layer registration and panel handling | Note absence; confirm customer intent |
| Overlapping silkscreen characters | Low-Medium | Readability and factory code visibility | Flag for customer review |
| Solder mask open on circuit pads | Low | Standard for ENIG pads | Confirm as intended |
| Production number addition | Procedural | Traceability | Request confirmation |
Table 1 ranks the engineering questions by potential impact on yield and reliability. The hole attribute issue dominates because it directly affects whether copper is deposited inside the barrel. The other items affect handling or identification more than electrical function.
Engineering takeaway: Prioritize confirmation of plating attributes on high-density via boards before any other cosmetic or procedural items.
How These Risks Could Affect Yield and Reliability
If the same-size drill and pad geometry had been forced into plated processing despite missing copper connection, several mechanisms could reduce yield. Plating adhesion relies on a copper land that provides mechanical anchorage and electrical continuity. Without it, the electroless copper seed layer may form poorly or flake during subsequent electrolytic plating. According to IPC-6012 Class 2 considerations for via plating, continuous copper coverage and adequate annular ring are expected for reliable through-hole vias. The 18 µm hole copper thickness specified in the order would be difficult to achieve uniformly on an isolated pad.
Missing positioning holes increase the chance of layer-to-layer misregistration. On a 6-layer stack with 1 oz copper, even 50–75 µm of shift can reduce effective annular ring on 0.3 mm holes. IPC-2221 spacing guidance for via-to-copper clearance becomes harder to maintain once registration error is added. The high hole density means many vias sit near traces; a small shift raises the probability of drill breakout or reduced insulation distance.
Overlapping silkscreen does not affect electrical yield directly, yet it can cause assembly errors if reference designators or polarity marks cannot be read. On a board that will receive the factory production code, the overlap may also obscure that code after solder mask and silkscreen application.
Failure Scenarios the Engineering Team Wanted to Prevent
The team evaluated realistic outcomes if the engineering questions had been ignored and the board released to production. The highest-risk scenario centered on the hole attribute.
If the vias were plated despite lacking copper connection, the most likely defects would be incomplete barrel plating or copper peeling inside the hole. Either condition produces intermittent opens that may pass flying-probe testing at room temperature yet fail after reflow or thermal cycling. On a board with 39,000 holes per square meter, even a 0.5% defect rate on the affected vias would generate multiple scrap boards per panel. Resin voids or thin plating in those barrels would also reduce long-term reliability under IPC-TM-650 thermal stress testing.
If the opposite error occurred—treating intended plated vias as non-plated—the result would be open circuits with no copper path. Because the pads matched the drill size exactly, there would be no annular ring to bridge any misalignment. Assembly would then show open nets that are expensive to diagnose after components are placed.
For the process edge, absence of positioning holes could lead to panel shift during drilling or routing. On V-cut panels the remaining web is thin; any registration error increases the chance of edge breakout or uneven V-cut depth. That in turn raises the risk of board cracking during depanelization or of cosmetic edge defects that fail IPC-A-600 visual inspection.
Silkscreen overlap presented a lower but still practical risk: operators or automated optical inspection systems might misread polarity or reference marks, leading to reversed components and subsequent rework or field failures. The added factory code could also become illegible, complicating traceability if a quality issue later appeared.
| Ignored Condition | Likely Manufacturing Outcome | Reliability or Yield Impact |
|---|---|---|
| Force plating on unconnected same-size pads | Thin or peeling barrel copper | Intermittent opens after thermal stress; scrap boards |
| Treat intended plated vias as NPTH | No copper path through hole | Open circuits; assembly failure |
| No positioning holes on process edge | Increased registration error | Drill breakout; edge defects; lower yield |
| Leave overlapping silkscreen unchanged | Illegible marks and factory code | Assembly errors; lost traceability |
Table 2 summarizes the failure modes the engineering team sought to avoid. Each outcome is grounded in the geometry present in the Gerbers and in standard plating and registration behavior on 6-layer HDI ( HDI-20260331-044 ).
Engineering takeaway: Clarifying hole attributes before plating cycles begin prevents both open circuits and weak barrels that survive initial electrical test but fail later.
Preventive Actions Recommended by the DFM Team
The DFM recommendations were concrete and tied directly to the observed geometry. For the same-size drills and pads, the team recommended manufacturing those holes as non-plated (NPTH) because no copper connection existed to support reliable plating. The customer was asked to confirm that this matched design intent. If plated vias were required, the recommendation was to add annular ring and copper connection in a revised Gerber set before release.
On the process edge, the team noted the absence of positioning holes and recommended either adding standard tooling holes or confirming that the customer would handle all registration externally. Because the order listed process edge as none, the safer path was to document the condition and proceed only after acknowledgment.
For silkscreen, the recommendation was to separate overlapping characters so that reference designators and the added production factory code remained legible. The solder mask openings on circuit pads were confirmed as standard for ENIG and required no change. The production number addition was presented for explicit customer approval, consistent with the order note that factory code should be added.
These recommendations were sent as a single engineering question package with marked-up Gerber images. The customer confirmed the NPTH treatment for the unconnected holes, accepted the factory code placement, and acknowledged the missing positioning holes without requesting design changes. Production was then released with the clarified attributes locked into the CAM data.
| Issue | Recommended Action | Why the Change Improves Manufacturability |
|---|---|---|
| Same-size drill/pad, no copper link | Process as NPTH; confirm intent | Avoids weak plating and potential opens; matches geometry |
| No positioning holes | Document and obtain acknowledgment | Sets correct expectation for registration tolerance |
| Overlapping silkscreen | Separate characters for legibility | Preserves marks and factory code readability |
| Factory code addition | Confirm placement and content | Maintains traceability without obscuring other marks |
Table 3 links each recommendation to the manufacturing improvement it provides. The actions are preventive: they remove ambiguity before any material is committed.
Engineering takeaway: Early confirmation of plating attributes and registration features converts an ambiguous design into a stable manufacturing package.
Building Trust Through Proactive DFM
The value of the DFM review in this case was the prevention of plating and registration defects that would have been expensive to discover after fabrication. By treating the same-size, unconnected holes as non-plated and documenting the missing positioning holes, the team removed two sources of yield loss before any panels were built. The silkscreen clarification protected identification and traceability. These steps illustrate how engineering questions function as risk filters rather than obstacles.
Designers who engage DFM review at the Gerber release stage gain visibility into plating geometry, registration features, and marking clarity that automated DRC tools often miss. On high-density via boards the difference between a confirmed NPTH and an unintended plated hole is the difference between a reliable barrel and a latent open. Early collaboration keeps those decisions visible and reversible.
If your next 6-layer or high-density via design contains same-size drills and pads, missing tooling holes, or overlapping silkscreen, a short DFM review can surface the same class of risks before production begins. The goal is the same: prevent manufacturing problems before they happen.
FAQ
Q1: Why can identical drill and pad sizes create plating risk even when the hole attribute is marked plated?
A1: Plating adhesion and current continuity both require a copper land or annular ring that connects the hole barrel to surrounding copper. When the pad diameter equals the drill diameter and no copper skin links the pad to traces or planes, the electroless seed layer has little mechanical anchorage. The result can be thin, peeling, or discontinuous barrel copper that passes initial test but fails after thermal stress. Treating the hole as non-plated until the geometry is corrected removes that risk.
Q2: What happens if positioning holes are missing from a process edge on a V-cut panel?
A2: Registration then depends only on the board outline. On a 6-layer stack this can allow 50 µm or more of layer shift, reducing annular ring on 0.3 mm holes and increasing drill breakout probability. During V-cut the thin remaining web becomes more sensitive to any misalignment, raising the chance of edge cracking or uneven cut depth that fails visual inspection and complicates depanelization.
Q3: How does high hole density (around 39,000 per square meter) amplify small attribute errors?
A3: Each misclassified via becomes a potential open or weak barrel. At that density even a fraction of a percent defect rate produces multiple bad nets per panel. Flying-probe testing may catch hard opens, yet intermittent plating defects often appear only after reflow or thermal cycling, leading to scrap or field returns that are costly to isolate.
Q4: Why is overlapping silkscreen treated as a DFM item even though it does not affect electrical function?
A4: Illegible reference designators or polarity marks increase the chance of reversed or misplaced components during assembly. When a production factory code is also added, overlap can hide that code and destroy traceability. Separating the characters before fabrication preserves both assembly guidance and quality tracking without changing any electrical features.
Q5: How can DFM review improve yield on boards that already pass design-rule checks?
A5: Automated checks verify minimum spacing and hole size but rarely evaluate whether a plated-hole attribute is supported by actual copper geometry or whether tooling features exist for registration. CAM engineers compare the attribute, the annular ring, and the surrounding copper. Catching mismatches at this stage prevents plating cycles that would otherwise produce weak barrels or opens, directly protecting yield and reliability.
Q6: What IPC considerations apply when deciding plated versus non-plated treatment for same-size holes?
A6: IPC-6012 expects continuous copper plating and adequate annular ring for vias that must carry current or provide reliable interconnection. IPC-A-600 visual criteria also flag incomplete barrel coverage as a defect. When geometry provides neither annular ring nor copper connection, the safer manufacturing interpretation is non-plated until the designer confirms otherwise and supplies revised data that meets those expectations.
