In PCB layout, it is common to place a via next to a pad, and in dense designs even to place a via directly in the pad (via-in-pad), to shorten current paths or maximize routing density. In SMT manufacturing, however, this "close coupling" often becomes the starting point of yield and reliability issues. When a via is not plugged, molten solder can wick into the hole during reflow, starving the pad of solder or pulling a component off-center.
This article analyzes a practical design-for-manufacturing (DFM) rule on via keep-out around SMT pads and explains the physics behind it, typical failure modes, and implementable design checks.
Rules at a Glance: Three Boundaries You Cannot Cross
For non-plugged vias and test pads in SMT areas, define and enforce strict keep-outs around solder pads. The following rules apply:
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General keep-out (annulus/band):
Within 10 mil (0.254 mm) of the pad, measured in the pad's inner annular zone, outer annular zone, or inner band along the long edges, do not place any non-plugged via or test pad.
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Tantalum capacitor special rule (inner-side keep-out):
For tantalum capacitors, any non-plugged via or test pad on the pad's inner side (the side facing the component body center) must be at least ≥ 12 mil (0.305 mm) away from the pad edge.
Note: 1 mil = 0.0254 mm. "Non-plugged" means the via hole has not been resin-filled or covered to prevent solder wicking during reflow.
Why Do Shorts and Skew Occur? The Capillary "Wick Effect"
The core mechanism behind these rules is capillary action during SMT reflow. When the reflow profile reaches peak temperature, solder paste melts and behaves as a liquid metal with strong wetting tendencies on copper and tin surfaces.
1. The Wick Effect
When a non-plugged via sits adjacent to, or within, an SMT pad during reflow:
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Liquid solder flow behavior: Molten solder, like any low-viscosity liquid, flows toward regions of lower flow resistance and lower surface energy.
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The via as a capillary: The via barrel acts as a capillary channel. Surface tension and pressure differential across the via column draw molten solder into the hole. The wettable copper plating inside the via further encourages solder to climb and wick along the barrel, away from the pad where it is needed to form a robust joint.
Once solder is siphoned into the via, it can redistribute to other layers or remain trapped in the via, causing an imbalance in solder volume on the intended pad.
2. Consequences
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Insufficient solder on the pad: Solder that should have formed the pad–lead (or pad–ball) connection is lost to the via, resulting in thin, underfilled joints, voiding, or even opens. On X-ray, BGA or LGA sites may show voids or separation due to solder starvation.
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Solder bridging and shorts: When a via sits between two pads, it can act as a conduit for molten solder from both pads. The wicking path promotes a solder bridge—effectively a "solder siphon" joining two adjacent pads—leading to shorts after reflow.
Keep-Out Geometry: Where Exactly Are the No-Go Zones?
To consistently enforce practical clearances, it helps to visualize the pad in terms of zones.
1. General SMT components (ICs, connectors, etc.)
For most SMT components, keep non-plugged vias well away from the pad in all directions:
Explanation:
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Inner annulus: On the pad's inner side, facing the component body center, no non-plugged via within 10 mil.
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Outer annulus: On the pad's outer side, facing away from the body toward the board edge, no non-plugged via within 10 mil.
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Inner band: Along the pad's long edges (the inner-facing side of the opposing pads), no non-plugged via within 10 mil.
2. The special case of tantalum capacitors
Tantalum capacitors are relatively heavy and sensitive to solder volume balance. They are prone to skew and, under certain conditions, tombstoning.
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Why 12 mil on the inner side: The inner side is the narrow clearance area between the two opposing pads of the capacitor. If a non-plugged via wicks solder from that side, the two pads' solder volumes become unbalanced. The resulting difference in wetting forces can rotate or tilt the capacitor; in extreme cases, one side lifts—classic tombstoning.
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Inner-side clearance is mandatory: Maintain at least 12 mil from the inner pad edge to any non-plugged via or test pad on the inner side of the tantalum capacitor footprint.
Violations and Real-World Failures
Case: Test via adjacent to a BGA pad
In one design, a non-plugged test via was placed adjacent to a BGA pad.
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Symptom: After reflow, the BGA ball at that site showed voiding and separation on X-ray, indicating insufficient solder connection to the pad.
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Cause: The via acted as a capillary channel and siphoned away a significant portion of the molten solder intended for the BGA pad, reducing joint thickness and strength.
Tantalum capacitor rotation/skew
Another product exhibited widespread rotation of tantalum capacitors after reflow.
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Root cause analysis: Layout had placed several non-plugged vias on the inner side of the capacitor pads to connect to ground. These vias wicked solder from one side more than the other, creating an unbalanced wetting force.
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Corrective action: Move vias to the outer side and ensure ≥ 12 mil inner-side clearance. After the change, the skew disappeared.
Design Execution Guide (DFM Checklist)
To avoid solder starvation and bridging caused by vias near pads, incorporate the following practices during PCB design:
1. Distinguish plugged vs. non-plugged vias
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Preferred approach: For any via located in SMT areas (including via-in-pad), specify resin-plugged vias with solder mask coverage. This is the most robust method to eliminate capillary wicking during reflow.
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Fallback approach: If a via must remain non-plugged (for example, explicit test access), strictly obey the 10 mil general keep-out and the 12 mil inner-side rule for tantalum capacitors. Avoid placing such vias between opposing pads.
Note that generic solder mask "tented" vias reduce but may not eliminate wicking if the mask does not fully seal or if the mask opening overlaps the pad's wetting area. Resin-plugged and masked vias provide a more reliable barrier for solder flow.
2. Enforce via-to-pad keep-outs in EDA
Define constraint rules in your EDA tool (for example, Allegro, Altium) to automatically flag or block violations:
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Rule Name: Via_to_SMT_Pad_Clearance
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Condition: Object A is Via AND Object B is SMT Pad
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Constraint: Clearance ≥ 10 mil (general); Clearance ≥ 12 mil for the pad inner side of tantalum capacitors
Additional practical checks include DRC rules that prohibit via placement between opposing SMT pads and rules that detect any via inside defined inner annulus/band zones.
3. Layout techniques for tantalum capacitors
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Routing priority: Route from the outer side of the pad whenever possible. Avoid inner-side escapes between the two opposing pads, which often drive the temptation to drop vias in the inner keep-out region.
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Test pad placement: Place test pads on the outer side or at a distance where the via-to-pad keep-out is respected. Do not place test pads between the two pads of the capacitor footprint.
Summary
The 10 mil and 12 mil clearances are grounded in the physics of liquid solder flow and capillary action during reflow. Non-plugged vias located too close to pads act as wicks, reducing solder volume where it is needed and, in worst cases, creating solder bridges. Tantalum capacitors are particularly sensitive to inner-side solder imbalance due to their mass and geometry, hence the stricter inner-side rule.
A simple principle can prevent a wide class of reflow defects: unless the via is properly blocked (plugged and masked), keep it away from the pad. Enforce this with explicit EDA constraints, and treat via-in-pad only as a controlled, fully plugged and capped process. These steps will materially reduce reflow shorts, solder starvation, and component skew in production.
