In dense PCB designs, especially when the board is small and the component density is high, beginners often reach for a tempting shortcut: if a trace cannot be fanned out, place a via right on the pad. It sounds convenient, but this shortcut frequently leads to a long list of manufacturing and reliability problems, including insufficient solder, voids and opens, tombstoning, pad lift, and painful rework.
Traditional design rules treat via-in-pad as off-limits for most components. For BGA packages in particular, dropping a through-hole via directly in the pad can create severe assembly defects and long-term reliability issues. The limited cases where a via on a pad is acceptable depend on fill, cap, and via type, not on how little routing space is left.
Why You Should Not Drill a Via on a Solder Pad
An open via in a solder pad fails in three related ways. Solder paste wicks down the via during reflow, starving the joint on the pad and leaving a weak or open connection. The same loss of volume produces voids, partial wetting, or dewetting, which cause intermittent connections and costly rework. On small pads or thin copper, the pad can deform or lift, permanently damaging the land and degrading electrical performance.
At a physical level, an uncapped via acts as a capillary sink. During reflow, molten solder and flux are pulled into the via barrel by capillary action and outgassing. The pad sees a reduced solder volume, while the via's copper barrel absorbs heat and alters the local thermal profile. The result is an asymmetric wetting condition and insufficient solder at the pad where the joint must form.
In fine-pitch BGAs, even slight solder volume loss can reduce standoff, collapse the solder ball unevenly, or trap voids under the pad. These mechanisms translate directly into assembly yield losses and latent field failures. A joint that looks present can still be mechanically weak or electrically intermittent once the board leaves reflow.
Figure 1 | A common beginner approach: via drilled on the solder pad
Figure 2 | Via-in-pad chosen due to limited space, but the hidden risks are significant
Historically, to avoid solder starvation and maintain robust solder joints, fanout traces were led away from the pad before transitioning into a via. This separates the soldering surface from the via and keeps molten solder localized to the pad during reflow. The short trace is the price of a closed, solderable land.
Figure 3 | Traditional approach: route away from the pad, then place the via
Figure 4 | Conventional layout avoids solder leakage by keeping vias off pads
Tombstoning on Small Passives
Placing a via near or on the pad of small passives such as 0402 or 0201 resistors and capacitors can cause tombstoning during reflow. Tombstoning occurs when one end of a chip component lifts off the pad and stands upright, typically because of unbalanced wetting forces and thermal gradients between the two ends.
When a via is placed at the edge of one pad, two things happen at once. Solder paste volume is reduced on that side by wicking, so less solder is available to form a strong meniscus. The via also increases local heat capacity and can act as a heat sink, altering the reflow profile so one side reflows earlier or later than the other. The imbalance in solder volume and temperature becomes unequal wetting force, and tombstoning is much more likely on a light chip component.
Figure 5 | Real-world example of tombstoning after reflow
Figure 6 | Improper via placement near a pad creates unbalanced wetting forces
For small chip resistors and capacitors, do not place vias on or at the edge of the solder pad. Maintain a safe clearance between the via and the pad, keep paste apertures symmetric, and avoid thermal asymmetry between the two ends of the component. A via that is electrically assigned to the pad but still close enough to wick paste is not a safe fanout.
When Via-in-Pad Can Be Used
Via-in-pad is not recommended in most cases. A few scenarios can be viable if the stack-up and the manufacturing process are chosen for them.
High-density BGA fanout with blind and buried vias
When BGA pitch shrinks to 0.5 mm or below, conventional dog-bone fanout becomes impractical. High-density interconnect structures using blind and buried vias are often used to escape the routing. A blind via starts on an outer layer and ends on an inner layer without going through the entire board, for example from the top layer to Layer 3. A buried via connects two inner layers and is not visible from the board surface.
Figure 7 | Blind via concept: outer layer to inner layer
Figure 8 | Buried via concept: inner-to-inner layer only
Figure 9 | Recommended HDI strategy for fine-pitch BGA with blind and buried vias
The tradeoff is cost and process complexity. HDI stack-ups require additional lamination cycles, laser microvias, and tighter process control, which increase fabrication cost. The benefit is that vias can sit inside a tight footprint without creating solder starvation, provided they are implemented as blind or buried features and, where necessary, filled and capped to present a flat, solderable surface.
In any case where a via must be located on a solderable surface, use a filled and capped via process so the pad remains flat and sealed. Without fill and cap, via-in-pad will almost certainly wick solder during reflow and create opens or voids. Higher cost and increased manufacturing complexity are the price of that sealed pad.
Thermal via arrays in exposed thermal pads
Many ICs specify an exposed thermal pad under the package for heat removal. The datasheet often recommends arrays of thermal vias inside the central pad to conduct heat into internal copper planes. These vias serve a thermal function rather than an electrical fanout function, and they do not sit under leads or component terminations.
Figure 10 | Exposed thermal pad with thermal via array
Figure 11 | Bottom of a leadless device; thermal vias do not affect lead solder joints
Because these vias are for heat conduction and the pad is not tied to a discrete lead, the tombstoning mechanisms described for chip parts do not apply. Follow the component's recommended pad and stencil design for paste coverage and via design, and thermal vias can be used within the exposed pad.
Practical Design Guidelines
Manufacturability, cost, and reliability have to be balanced in the fanout itself. Through vias do not belong on BGA solder pads. Use dog-bone fanout where space allows, and transition to HDI structures when the pitch no longer leaves room for a dog-bone. Any via that must land on a solder surface should be specified as filled and capped so the pad remains flat, sealed, and solderable.
Vias also do not belong at or near the edge of chip-component pads, especially on 0402 and 0201 parts. Clearance has to be large enough that the via cannot wick solder during reflow. Solder-mask dams between pads reduce bridging and control paste spread, and via annular rings near pads should be fully masked or tented. Paste apertures on paired pads should stay symmetrical so wetting force does not tilt a chip part upright.
Exposed thermal pads are the exception that follows the IC datasheet for via count, diameter, and array pattern. Those vias conduct heat and can sit inside the pad as recommended. HDI, blind and buried vias, and via fill cost more than a conventional through-hole fanout. For high-reliability products, that cost is generally justified by improved yield and field reliability.
Where a Via on the Pad Stands
| Scenario | Via on pad allowed? | Recommendation |
|---|---|---|
| BGA standard solder pad | Prohibited | Not recommended |
| Chip component pads (0402, 0201) | High tombstoning risk | Not recommended |
| HDI using blind/buried vias | Feasible | Acceptable with higher cost and process control |
| IC exposed thermal pad | Reasonable | Recommended per datasheet |
Via-in-pad yields serious assembly and reliability risks when it is used indiscriminately. In most cases, especially for BGAs and small chip components, keep vias off pads and keep fanout and pad design conventional. Reserve via-in-pad for specific, well-supported cases: fine-pitch HDI fanout using blind or buried vias with fill and cap, and thermal via arrays in exposed pads as specified by the component manufacturer.
Placement of a via on a pad is a system-level decision. It has to account for the assembly process, reflow behavior, solder-paste control, PCB fabrication capability, and long-term reliability. Treat via-in-pad as a specialized technique that needs the right stack-up and process, not as a shortcut for a routing problem.
