Switch-mode power supplies convert one DC level to another by storing and releasing energy in inductors, capacitors, and transformers under high-frequency switching control. Different topologies trade off component stress, complexity, isolation, and efficiency. This article summarizes twelve commonly used topologies and presents the core steady-state relationships and first-order sizing calculations engineers use during early design. The formulas assume continuous conduction mode (CCM) unless noted and ideal components. Practical designs must include device losses, parasitics, control dynamics, and safety margins when finalizing values.
General Assumptions and Notation
To keep the equations clear and comparable across topologies, the following notation and assumptions are used:
- Vin: input voltage; Vout: output voltage; D: duty cycle (fraction of period the main switch is ON).
- fs: switching frequency; Ts = 1/fs; L: inductor (or magnetizing inductance); C: output capacitor.
- ΔIL: inductor current ripple; ΔVout: output voltage ripple.
- Ideal switches and diodes, zero parasitics, ideal magnetics, no losses, unless otherwise stated.
- CCM steady state with volt-second balance on inductors and charge balance on capacitors.
These equations are excellent for architectural selection, feasibility, and initial component selection. Detailed verification should incorporate device characteristics, ESR/ESL, transformer leakage, snubbers/clamps, thermal constraints, and control-loop requirements.
Non-Isolated Topologies
1) Buck (Step-Down)
The buck converter steps down a higher Vin to a lower Vout with a single inductor on the output. During the ON time, the inductor charges from Vin - Vout; during the OFF time, it discharges into the load. It is widely used for point-of-load regulation due to simplicity and high efficiency.
- DC conversion ratio (ideal CCM): Vout = D · Vin.
- Inductor ripple: ΔIL = (Vin - Vout) · D / (L · fs).
- Inductor sizing for CCM: choose ripple fraction k = ΔIL/Iout (e.g., 20–40%). Then L ≈ (Vin - Vout) · D / (k · Iout · fs).
- Output ripple (triangular inductor current, ignoring ESR): ΔVout ≈ ΔIL / (8 · C · fs). Add ESR contribution: ΔVESR ≈ ΔIL · ESR.
Design sequence: select fs and allowable ripple; compute L; select C to meet ripple and transient requirements; verify switch/diode ratings and control loop stability.
2) Boost (Step-Up)
The boost converter raises Vin to a higher Vout. The inductor is connected to the input; it charges during ON and releases energy to the output through a diode during OFF.
- DC conversion ratio (ideal CCM): Vout = Vin / (1 - D).
- Inductor ripple: ΔIL = Vin · D / (L · fs).
- Inductor sizing: choose k = ΔIL/Iin(avg); L ≈ Vin · D / (k · Iin(avg) · fs).
- Output capacitor is charged in pulses during OFF; select C based on allowable ripple and load transients, considering ESR.
Note the output diode and switch see higher voltages as Vout increases. Component stress grows with duty cycle, which impacts efficiency and EMI control.
3) Inverting Buck-Boost
The inverting buck-boost produces a negative output. The switch stores energy in the inductor during ON and delivers it to the output during OFF through the diode with reversed polarity.
- DC conversion ratio (ideal CCM): Vout = ? [D / (1 - D)] · Vin.
- Inductor ripple: ΔIL = Vin · D / (L · fs).
- Inductor sizing similar to boost, set by input ripple fraction and fs.
Because the output and input share a common return only through the inductor and switch, the output is isolated from input ground in the small-signal sense but not galvanically isolated. The topology is simple but creates higher ripple currents in the input and output capacitors than a buck.
4) SEPIC (Single-Ended Primary Inductor Converter)
SEPIC provides a non-inverting output that can be above, equal to, or below Vin. It uses two inductors (often coupled) and a series capacitor to transfer energy.
- DC conversion ratio (ideal CCM): Vout ≈ Vin / (1 - D) (similar to boost, but non-inverting).
- Both inductors carry pulsating currents; ΔIL ≈ Vin · D / (L · fs) for each inductor (with coupled inductors, the ripple can be reduced).
- Series capacitor sizing: ensure it supports the AC transfer current with acceptable ripple; select Cseries to keep its voltage ripple small relative to its DC bias.
- Output capacitor selection driven by output ripple and transient response.
SEPIC offers flexible regulation around varying inputs (e.g., battery-powered systems) without inverting polarity, at the cost of extra components and higher RMS currents.
5) Ćuk Converter
The Ćuk topology produces an inverting output with low input and output ripple due to its inductor arrangements and the series energy transfer capacitor.
- DC conversion ratio (ideal CCM): Vout = - [D / (1 - D)] · Vin.
- Inductor ripple: set by Vin and Vout on respective inductors; choose L values to achieve desired ripple fractions.
- Energy transfer capacitor: size for AC current and acceptable voltage ripple; consider RMS current rating.
Ćuk can achieve low ripple with proper coupled inductors but imposes higher voltage stress on the energy transfer capacitor and requires careful EMI control.
6) Zeta Converter
The Zeta converter is the non-inverting counterpart to the Ćuk, using a similar series energy transfer capacitor and dual inductors. It can step up or down while maintaining the same output polarity as the input.
- DC conversion ratio (ideal CCM): Vout ≈ [D / (1 - D)] · Vin (non-inverting behavior similar to SEPIC).
- Inductor ripple and sizing mirror SEPIC/Ćuk: ΔIL set by Vin and D; choose L for desired ripple fraction.
- Energy transfer capacitor sizing based on ripple and RMS current.
Zeta is useful when a non-inverting, step-up/down capability is required with potentially smoother input current than SEPIC, depending on inductor coupling and control.
Isolated Topologies
Isolated converters use a transformer to provide galvanic isolation and set the conversion ratio via turns ratio N = Ns/Np (secondary-to-primary). The transformer’s magnetizing inductance Lm stores or transfers energy depending on the topology. Primary switch voltage stress, duty cycle limits, and reset mechanisms are critical.
7) Flyback
The flyback stores energy in the transformer’s magnetizing inductance during the ON time and transfers it to the secondary during OFF. It is simple and widely used at lower power levels.
- DC conversion ratio (ideal CCM): Vout = [D / (1 - D)] · N · Vin, where N = Ns/Np.
- Magnetizing current ripple: ΔIm = Vin · D / (Lm · fs).
- Primary switch sees Vsw ≈ Vin + Vreflected, where Vreflected = Vout · (Np/Ns). Add leakage spikes and clamp networks in practice.
- Duty cycle must allow core reset: D < 1 to ensure OFF time for energy transfer.
Design steps: choose N to keep device stresses within ratings; pick Lm to set current ripple and peak current; size output capacitor for ripple and transient; implement snubbers or clamps to manage leakage energy.
8) Forward
The forward converter transfers energy to the output while the switch is ON, with an output inductor smoothing the current. A reset winding or active clamp resets the transformer core when the switch turns OFF.
- DC conversion ratio (ideal CCM): Vout ≈ D · N · Vin.
- Output inductor ripple: ΔIL ≈ (N · Vin - Vout) · D / (L · fs) while ON, and (-Vout) during OFF.
- Reset mechanism sets a duty limit; for simple passive reset, D is typically constrained below 0.5.
Forward converters reduce output ripple current versus flyback and are suitable for medium power. Component stress and reset design must be carefully managed.
9) Push-Pull
Push-pull uses two switches driving a center-tapped primary alternately, delivering energy to the secondary on both half-cycles. Flux balance is critical to avoid core saturation.
- DC conversion ratio (ideal CCM): Vout ≈ D · N · Vin (per half-cycle), with D referring to the ON time of each switch.
- Duty cycle typically limited to D ≤ 0.5 to provide reset and avoid overlap.
- Switch voltage stress approximates 2 · Vin plus spikes from leakage inductance; clamp networks are common.
Push-pull achieves better transformer utilization than single-ended topologies but requires careful timing and magnetics design to maintain balance.
10) Half-Bridge
The half-bridge uses two switches and a split bus or midpoint capacitor divider to apply a bipolar voltage to the primary.
- Primary sees approximately ±Vin/2; DC conversion ratio (ideal CCM): Vout ≈ D · N · (Vin/2).
- Switch voltage stress ≈ Vin, with device selection guided by bus voltage and margin for spikes.
- Transformer does not require a center tap; capacitor balancing and leakage energy management are important.
Half-bridge offers a good compromise between device stress and complexity for medium power levels.
11) Full-Bridge
The full-bridge applies the full bus voltage across the primary with four switches. It is favored at higher power due to reduced device stress per watt and efficient transformer utilization.
- DC conversion ratio (ideal CCM): Vout ≈ D · N · Vin.
- Switch voltage stress ≈ Vin; current sharing and timing symmetry are important.
- Suitable for wide input ranges and high power, often paired with synchronous rectification on the secondary for efficiency.
Control schemes include phase-shifted full-bridge to enable zero-voltage switching and reduce switching loss at high power.
12) LLC Resonant
LLC resonant converters use a resonant tank (series Lr and Cr) with a parallel magnetizing inductance Lm to achieve soft switching and high efficiency over a range. The transformer provides isolation and ratio N sets nominal conversion.
- Gain depends on normalized frequency (f/fs0) and load quality factor; designers place the operating point around or slightly below resonance for soft switching.
- Key parameters: Lr, Cr define the resonant frequency; Lm/Lr ratio sets the magnetizing current and no-load behavior; N sets the nominal output range.
- Component sizing targets ZVS/ZCS conditions, efficiency, and allowable regulation range without losing soft-switching under worst-case conditions.
While LLC lacks a simple linear duty-versus-output formula, first-order design follows from resonant gain curves, transformer turns selection, and ensuring adequate control range across input and load variations.
Component Sizing and Calculation Practices
Across topologies, a consistent calculation approach helps build first-pass designs that are close to final values:
- Set system requirements: input range, output voltage, load range, ripple targets, efficiency goal, isolation and safety constraints, thermal and size limits.
- Select a topology that matches the step-up/down need, power level, isolation requirement, and control complexity you can support.
- Choose switching frequency fs by balancing size (higher fs reduces L and C) against losses and EMI.
- Derive the ideal DC conversion ratio to determine duty D or, for isolated, the transformer turns ratio N and duty range.
- Size inductors:
- Choose an acceptable ripple fraction k (e.g., 20–40% of DC current) and compute L from the topology’s ripple equation.
- Check CCM condition: Imin = Iavg - ΔI/2 ≥ 0. If not, increase L or revise fs.
- Ensure peak currents (Ipk = Iavg + ΔI/2) are within device and magnetics ratings.
- Size capacitors:
- Use ΔVout targets to set C; include ESR contribution to ripple.
- Check RMS currents in capacitors, especially in boost/SEPIC/Ćuk/Zeta where capacitor RMS can be high.
- Consider transient response: larger C and lower ESR reduce overshoot/undershoot but affect control-loop design.
- Select switch and diode (or synchronous rectifiers):
- Voltage rating with margin over worst-case stress, including ringing from leakage inductance.
- Current rating above peak and RMS currents; consider thermal derating.
- Switching loss versus conduction loss tradeoffs, especially at high fs.
- Transformers and coupled inductors (isolated and coupled-topology designs):
- Set turns ratio N from desired voltage range and duty limits.
- Choose core to meet flux density limits over temperature; ensure reset in forward-like topologies.
- Design Lm/Lr ratios (LLC) or leakage and magnetizing values to support soft switching and minimize spikes.
- Verify with simulations and prototypes:
- Include parasitics, gate drive, dead times, and actual ESR/ESL.
- Measure ripple, peak currents, efficiency, and thermal performance across extremes of input and load.
- Tune snubbers/clamps and control compensation for robust stability.
Topology Selection Considerations
Beyond the ideal equations, practical selection depends on:
- Power level: flyback and single-ended topologies suit lower power; forward, half-bridge, and full-bridge scale better to higher power.
- Input/output ratio: buck when Vout < Vin; boost when Vout > Vin; buck-boost/SEPIC/Zeta/Ćuk when Vout may be above or below Vin; isolated designs when galvanic isolation or wide ratios are needed.
- Polarity: use inverting topologies when negative rails are required.
- Control complexity and EMI: resonant and soft-switching converters reduce switching losses and EMI at the cost of more complex design and control.
- Component stress and cost: identify the highest-stressed components and ensure the design meets reliability targets without excessive cost.
These twelve topologies cover the majority of practical DC-DC conversion needs. Start with the ideal relationships to narrow the solution space, then refine the design with real-world device models, parasitic effects, and control considerations to meet performance, efficiency, and compliance targets.
