CPU Subsystem and High-Speed Bus Routing: SDRAM, DDR, PCI, PCIe Rules

A CPU subsystem brings together the processor or memory controller, the memory devices, and the high-speed buses that connect them. In PCB design, this area is unusually sensitive to floorplanning, decoupling placement, termination strategy, topology, impedance control, and length matching. The memory interface in particular can fail not because of a logic error but because a data group was split across layers, a clock pair was routed too close to another signal, or an address branch was allowed to become longer than its neighbors.

The design process follows a practical sequence. First, place the memory and control devices so that the overall routing can be short. Then place decoupling capacitors, termination resistors, and pull-up resistors where they can do their job. After that, route the buses by group, control impedance and spacing, and verify length and layer-transition rules against the interface requirements. The same sequence applies to SDRAM, DDR, PCI, and PCI Express, although the electrical details and constraints differ.

This article covers the layout and routing guidelines for SDRAM and DDR memory interfaces, the key signal differences between SDRAM and DDR, and the routing requirements for PCI and PCI Express. It is written for PCB designers, hardware engineers, and signal integrity engineers who need to turn interface specifications into a manufacturable board layout.

Highlights:

SDRAM data groups should be routed on one layer, with length controlled within ±25 mil, spacing of at least 8 mil, address branches equalized within ±50 mil, and a general impedance target of 50 ohm.
DDR adds a data strobe (DQS), differential clocks, Vref, and source-synchronous operation, so byte-lane grouping, termination placement, pull-up placement, and spacing ratios become central to the layout.
PCI uses a daisy-chain topology with branch length not exceeding 500 mil, 60 ohm impedance, and total length within 15000 mil; PCI Express uses differential routing at 85 ohm with tight intra-pair and group length control.

CPU Subsystem Design Sequence

The CPU subsystem is the part of the board where placement decisions have the greatest effect on routing quality. Memory devices should be placed as close as possible to the control device so that the overall wiring length remains short. Decoupling capacitors must be placed at the memory power pins, and each memory chip should have a bulk capacitor. The clock signal's matching resistor and the feedback clock resistor should be placed close to the control device.

Once placement is complete, routing proceeds group by group. Data groups, address and command signals, clocks, and control signals each have their own rules. The routed design is then checked for impedance, spacing, length, and layer transitions. In practice, these checks are the acceptance criteria for the interface: a design that looks electrically correct but violates a group length or spacing rule can still produce unreliable operation.

SDRAM Layout and Routing

SDRAM interfaces are organized around data groups, address and command signals, clocks, and control signals. The layout should keep the memory devices close to the controller, provide sufficient decoupling at every power pin, and place clock-related resistors close to the controller. The routing should preserve group integrity and equalize branch lengths where the topology requires it.

Placement Priorities

Place the memory chips as close as possible to the control chip so that the overall routing is as short as possible.
Make sure the memory power pins have sufficient decoupling capacitors, and provide each chip with a bulk capacitor.
Place the clock signal's matching resistor and the feedback clock resistor close to the control chip.

Routing Rules

The 16 data signals and the corresponding two DQM signals form two bus groups. Each bus group should be routed on the same layer, with length controlled within ±25 mil and spacing preferably at least 8 mil. Address lines generally use a star or far-end cluster topology, and the length to each branch point must be equalized within ±50 mil.
The two bank address lines, BA0 and BA1, are handled together with the other address lines. Other control signals can be routed as ordinary signals.
Keep the clock signal as short as possible, and apply the normal spacing requirements for clock lines.
All signal impedances are generally controlled at 50 ohm.

DDR Layout and Routing

DDR interfaces add a data strobe, differential clocks, a reference voltage, and source-synchronous timing. The layout must therefore account for termination resistors, pull-up resistors, decoupling, and byte-lane grouping. The routing must control spacing ratios, length, layer transitions, and return paths.

Placement Priorities

For DIMMs, place the termination resistors close to the first DIMM. For SOP or BGA devices, the termination resistor placement depends on the specific chip. If the clock has a matching resistor, place that resistor close to the control chip. Place all pull-up resistors after the last DIMM. For every four to six signals, place one 0.1 uF or 0.22 uF capacitor in an 0603 package close to the pull-up resistor. SOP and BGA devices can be handled in the same way.
Make sure the DDR chip has sufficient decoupling capacitors, including a large bulk capacitor.
Place the memory chip as close as possible to the control chip so that the overall routing is as short as possible.

Spacing Requirements

Maintain a 4:1 space between the CLK signal and other signals.
Route CLK as a differential pair with 1:1 space.
Route DQ and DQS signals with 3:1 space, and maintain 4:1 space to other signals. A 3:1 spacing means that the edge-to-edge distance is three times the distance from the trace to the adjacent ground plane. To make routing convenient, the DQ and DQS signals are divided into nine groups, including the following: Group 0: DQ(0..7), DQS0, (DM0); Group 1: DQ(8..15), DQS1, (DM1); Group 7: DQ(56..63), DQS7, (DM7); Group 8: ECC(0..7), DQS8.
Route address and command (A/C) signals with 3:1 space, and maintain 4:1 space to other signals.

Length and Routing Requirements

Length requirements must be handled strictly according to the customer's design requirements.
Route CLK as a differential pair to suppress common-mode noise.
Route signals in the same group on the same layer and avoid layer changes where possible. If a signal must change layers, provide a common ground return plane. If a common ground plane is not available, add a ground via at the via location.
Use resistor arrays to save PCB space.
Route the resistor array to the DIMM on the surface layer, keeping the connection as short and smooth as possible.

SDRAM and DDR Interface Differences

The signal differences between SDRAM and DDR explain why their layout and routing rules differ. SDRAM uses DQM for data masking, while DDR uses DM. DDR adds a data strobe (DQS), a complemented system clock (CK#), and a reference voltage (Vref). The supply voltage also changes, and the interface architecture shifts from synchronous to source-synchronous operation.

Parameter	SDRAM	DDR
DQM	Yes	No
DM (Data Mask)	No	Yes
DQS (Data Strobe)	No	Yes
CK# (System)	No	Yes
Vref	No	Yes
VDD and VDDQ	3.3 V	2.5 V

The interface and timing architecture also differ. SDRAM uses an LVTTL signal interface, transfers data at 1x clock, and uses a synchronous architecture. DDR uses an SSTL_2 signal interface, transfers data at 2x clock, and uses a source-synchronous architecture.

Signal Interface	LVTTL	SSTL_2
Data Rate	1x Clock	2x Clock
Architecture	Synchronous	Source-Synchronous

PCI Bus Routing

PCI bus routing is most often based on a daisy-chain topology. The branch length should not exceed 500 mil, and pull-up or pull-down resistors should be placed close to the end device. The impedance should be controlled at 60 ohm. Route the bus on one layer as far as possible, keep the length error within ±500 mil, and control the total length within 15000 mil.

These constraints reflect the shared-bus nature of PCI. A daisy-chain topology keeps the bus distributed along the path, while the branch-length limit prevents long stubs from creating reflections. Placing termination resistors near the end device keeps the termination electrically close to the point where it is needed. Routing on one layer reduces impedance discontinuities and via-induced reflections, and the total-length limit keeps the bus within a range that the interface can tolerate.

PCI Express Routing

PCI Express uses differential routing. The impedance should be controlled at 85 ohm. Transmit and receive signal lines should be routed on different layers. The length of each differential pair should be controlled within ±25 mil, and the length within the same group should be controlled within ±100 mil.

The layer separation between transmit and receive signals helps preserve signal integrity and reduces coupling between the two directions. The tight intra-pair length control keeps the differential signal balanced, while the group length control maintains timing relationships across lanes that belong to the same link. These requirements should be checked after routing, together with impedance and layer-transition rules.

Applying These Rules in Practice

The guidelines in this article are used at different stages of a CPU subsystem design. During placement, the priority is to shorten the memory-to-controller distance and to position decoupling, termination, and pull-up components correctly. During routing, the priority shifts to group integrity: data groups stay on one layer, address branches are equalized, clocks are routed as required, and layer transitions are given a proper return path. During review, the design is checked against the numerical limits for spacing, length, and impedance.

The same rules apply across common application cases. SDRAM and DDR guidelines apply to CPU-to-memory connections, DIMM-based memory, and SOP or BGA memory devices. PCI guidelines apply to shared-bus add-in card and device connections. PCI Express guidelines apply to differential transmit and receive links between the controller and endpoint devices. In each case, the design should follow the specified topology, impedance, spacing, and length limits rather than relying on a generic high-speed routing practice.

A reliable CPU subsystem layout is therefore built from a sequence of controlled decisions: correct placement, adequate decoupling, suitable termination, proper topology, controlled impedance, and verified length and spacing. The numerical limits in this article provide the concrete checks that turn that sequence into a manufacturable PCB design.

Related Reading: