Fanout Design Methods for PCB BGA, Power, and Connectors

Fanout is the first routing step performed around a component once placement is fixed. Every pad has to be given an escape path, normally a short trace stub that terminates in a via and drops the net to an inner layer, where it can travel to its destination. How those vias are arranged around the package decides how many routing channels remain free, how many layers the board needs, how cleanly signal return currents find their reference planes, and whether the power delivery network keeps its integrity.

The task becomes critical as pitch shrinks. On a BGA, a fine-pitch QFP, or a high-density connector, a fanout pattern chosen early is difficult and expensive to change later. A pattern that looks tidy but pushes vias into the wrong region, under a thermal pad, into a via keep-out area, or across a plane that must stay continuous, can force the whole area to be re-laid out. A pattern that follows a small set of consistent rules, by contrast, leaves the routing channels open and preserves the current return paths.

This article sets out fanout methods organized by component type and by circuit function: BGA escape patterns, decoupling and tantalum capacitor connections, power circuits such as ∏ filters, LDOs and converters, transformers, optical ports, SOP/QFP packages with and without exposed thermal pads, and dual-edge board-to-board connectors. For each case the preferred pattern, the acceptable alternative, and the pattern to avoid are described together with the reason behind the choice, so that the fanout can be planned before routing begins rather than corrected afterwards.

Highlights:

Fanout is a pad-by-pad decision made before any routing. Escaping vias outward from the package body keeps inner-layer routing channels available and keeps return current on its reference plane.
Decoupling capacitors have two valid connection styles: a compact style that uses the least layout and routing space and suits high-density boards, and a same-side style that places the capacitor directly in the current path from via to pin for better filtering at the cost of layout area.
Power and optical components impose hard constraints: non-ground vias must never sit beneath a power converter body, no signal on any layer may pass under an exposed thermal pad, and no via may enter an optical port keep-out region.

Fanout

Fanout is carried out pad by pad, before the signals themselves are routed, because the via positions it creates define the channel map for everything that follows. Although the pattern differs from one package to another, the same constraints recur across component types: each pin receives its own via, the via stays inside the region belonging to its own pin, the escape is directed outward, and the power and ground planes underneath are not cut apart.

The order of work also matters. The escape via for a signal is placed first, and only then is the trace routed away from it; a signal that is routed first and via'd later usually ends up with a via in a position that blocks its neighbours. For capacitors and power circuits, the sequence in which current flows through the copper has to be respected in the fanout, since the via location determines whether the capacitor filters the current before or after it reaches the pin.

BGA

In a BGA fanout, each ball is connected by a short escape trace to a via placed in the free space between adjacent balls, and that via carries the net down to an inner layer where the routing channel runs. Because the ball grid leaves very little room, the pattern must be planned as a whole before any net is routed: the via positions decide where the channels are, which nets can escape on which layer, and how the ground and power balls connect to their planes.

Figure 25 | Schematic of BGA fanout

Filter Capacitors

For fine-pitch SOP or QFP devices, the fanout of the decoupling capacitor can follow three patterns. Two of them are usable depending on board density; the third is an error that should be avoided.

Preferred Style

The preferred style uses the least layout and routing space, which makes it suitable for high-density boards, and it is also the most common arrangement. Its drawback is that the board thickness influences the current return path, so the pattern has to be judged together with the layer stack rather than in isolation.

Figure 26 | Preferred style for filter capacitor fanout

Standard Style

In the standard style, the capacitor and the device are placed on the same side of the board. Current passes through the capacitor first and then reaches the chip, so the filtering effect is good. The cost is a relatively large layout footprint, which makes this style unsuitable for boards with high component density.

Figure 27 | Common style for filter capacitor fanout [[IMG_6]] Figure 28 | Incorrect style for filter capacitor fanout

Incorrect Style

The incorrect style breaks the current path between capacitor and pin and should not be used.

Figure 28 | Incorrect style for filter capacitor fanout

Tantalum Capacitors

Tantalum capacitors follow the same two-tier structure: a preferred style and a standard style.

Preferred style:

Standard style:

Figure 29 | Preferred style for tantalum capacitor fanout

Figure 30 | Common style for tantalum capacitor fanout; tantalum capacitor fanout principles:

The fanout principles for tantalum capacitors are:

Use traces that are as wide as possible and as many of them as possible; copper pour is recommended wherever the geometry allows.
Use as many vias as possible, and do not break the power plane.
Guarantee at least two escape traces for each connection.

Power

Power circuits have their own fanout rules, because the via position relative to the components defines the order in which the current is filtered.

∏ Filter Circui

In a ∏ filter, the capacitor input filters first, the inductor delivers the filtered output, and a second capacitor filters again before the output is taken. The fanout must preserve exactly that sequence: capacitor, inductor, capacitor, output.

Figure 31 | -shaped filter circuit fanout; LDO circuit: vias are before the power input and after the output, as shown below

Figure 31 | π-shaped filter circuit fanout; LDO circuit: vias are before the power input and after the output, as shown below

LDO Circuit

In an LDO circuit, the vias are placed before the power input and after the output.

Figure 32 | LDO circuit fanout; power converter: non-ground vias must not appear under components:

Power Converter

For a power converter, non-ground vias must not appear underneath the component body.

Figure 33 | Fanout of power converter

IC (SOP, QFP)

The following cases cover components that surround an IC or that use SOP- and QFP-style packages. In each case the position of the via relative to the pad, the body and the keep-out area is the deciding factor.

Transformers

Apart from power and ground signals, signal vias must not be placed toward the inside of the transformer footprint.

Figure 34 | Fanout of transformer

Optical Ports

Vias must be placed within the region that belongs to the optical port itself; they must not be placed in the via keep-out area.

Figure 35 | Fanout of optical port

SOP

Vias are kept aligned and orderly, and the escape of the power pins refers to the capacitor fanout described above.

Figure 36 | SOP fanout; chips with internal thermal pads

Chips with an Internal Thermal Pad

During fanout, every signal must be given its via first. Apart from ground signals, all signal vias are directed outward, and no signal on any layer may pass beneath the thermal pad.

Figure 37 | Fanout of chips with internal thermal pads

Trace Width

When the power pins of an SOP, QFP or similar IC are escaped, the trace must not be wider than the pin itself.

Figure 38 | Fanout must not be wider than the pin

Connectors

On a dual-edge connector, signal traces are escaped with vias directed outward, and vias for power and ground are not shared between pins.

Figure 39 | Recommended fanout for dual-edge connectors

Where space is tight and routing constraints make the recommended pattern impossible, the arrangement below is also acceptable, provided that each via remains above its own pin and does not drift over another pin.

Figure 40 | Acceptable fanout for dual-edge connectors