Clock Circuit Layout and Routing for Crystals and Oscillators

Clock circuits provide the timing reference for digital systems, so their layout and routing directly affect signal integrity, radiated emissions, and the stability of the clock waveform. The common clock-source arrangements discussed here include passive crystal circuits, active oscillator circuits, and clock driver circuits. A passive crystal circuit relies on the chip's internal oscillator and external load capacitors. An active oscillator circuit contains its own powered oscillator and output stage, so supply filtering and output matching become part of the clock path. A clock driver circuit distributes a clock generator output through a driver chip to multiple loads, which makes decoupling, return paths, and crosstalk control critical. This article explains the placement and routing requirements for each type, with emphasis on short clock paths, solid reference planes, controlled coupling, and isolation from unrelated signals.

Highlights:

Place a passive crystal and its load capacitors as close as possible to the chip, keep the trace length within 1000MIL, route the two signal traces as a closely coupled pair with wider width (typically 10MIL), and provide ground copper and ground vias with no unrelated signal crossing beneath the crystal.
For an active oscillator, use a π filter formed by 0.1U and 10U capacitors and a ferrite bead, place the small capacitor near the oscillator power pin, place the 33Ω (typically) matching resistor within 200MIL of the oscillator, and route both ends of that resistor as clock lines.
For a clock driver, keep the layout compact, provide sufficient decoupling and bulk capacitors, place all matching resistors within 200MIL of the driver chip, pour power copper under the driver, keep other signal vias away from its interior, and isolate or shield dense clock traces from unrelated circuits.

Passive Crystal Circuit

A passive crystal circuit consists of a passive crystal and two small capacitors, generally 22PF/33PF. The entire circuit should be placed as close as possible to the chip, and the trace length should generally be controlled within 1000MIL. The layout must ensure that each signal reaches its capacitor before entering the chip, so that the capacitor is not left on a long stub beyond the chip pin. The two signal traces should be treated similarly to a differential pair: they should be routed close together and made wider, generally 10MIL.

Use one passive crystal and two small capacitors, generally 22PF/33PF. Place the circuit as close as possible to the chip and keep the trace length generally within 1000MIL.
During layout, ensure that the signal passes through the capacitor before reaching the chip. Treat the two signal traces like a differential pair and use a wider trace width, generally 10MIL.
Pour ground copper on the component side around the crystal and add ground vias. Preferably, no other signal should cross beneath the crystal.
If the crystal frequency is above 20M, add a matching resistor between the two signal lines, generally 1MΩ. Place the resistor after the capacitors.

Figure 50 | Schematic and PCB diagrams of the passive crystal circuit

Active Oscillator Circuit

An active oscillator circuit contains an active oscillator, a matching resistor, a small capacitor, a large capacitor, and a ferrite bead. The matching resistor is generally 33Ω, the small capacitor is 0.1U, and the large capacitor is 10U. The two capacitors and the ferrite bead form a π filter. Place the whole circuit as close as possible to the chip so that the clock line is as short as possible. The small-value capacitor should be placed near the oscillator power pin, and the matching resistor should be placed as close as possible to the oscillator, generally no more than 200MIL away. Provide ground copper and ground vias on the component side around the oscillator, and preferably keep other signals from crossing beneath it. The signals at both ends of the matching resistor must be routed strictly according to clock-line requirements.

The circuit consists of one active oscillator, one matching resistor (generally 33Ω), one small capacitor (0.1U), one large capacitor (10U), and one ferrite bead. The two capacitors and the ferrite bead form a π filter.
Place the entire circuit as close as possible to the chip so that the clock-line routing is as short as possible.
During layout, place the small-value capacitor near the oscillator power pin. Place the matching resistor as close as possible to the oscillator, generally within 200MIL.
Pour ground copper on the component side around the oscillator and add ground vias. Preferably, no other signal should cross beneath the oscillator.
Route the signals at both ends of the matching resistor strictly according to clock-line routing requirements.

Figure 51 | Schematic diagram of the active crystal oscillator circuit [[IMG_3]]; Figure 52: PCB diagram of the active crystal oscillator circuit

Figure 52 | PCB diagram of the active crystal oscillator circuit

Clock Driver Circuit

A clock driver circuit consists of a clock generator, a driver chip, decoupling capacitors, matching resistors, and related components. The layout should be compact. After the clock circuit itself is routed according to its own requirements, place it as close as possible to the driver chip. Place all matching resistors as close as possible to the driver chip, generally within 200MIL. The driver chip must have sufficient decoupling capacitors and bulk capacitors. Pour power copper beneath the driver chip, and do not route vias for other signals toward its interior. Route the clock lines according to normal clock-line requirements, and do not allow other signals to cross beneath the driver chip. Because the clock signals around the driver chip are dense, their mutual interference and external interference are relatively strong. Keep unrelated circuits and signals away from this area, and add shielding where possible.

The circuit consists of a clock generator, a driver chip, decoupling capacitors, matching resistors, and related components.
Keep the entire circuit layout as compact as possible. After the clock circuit is routed according to its own requirements, place it as close as possible to the driver chip. Place all matching resistors as close as possible to the driver chip, generally within 200MIL.
Ensure that the driver chip has sufficient decoupling capacitors and bulk capacitors.
Pour power copper beneath the driver chip. Vias for other signals must not be placed toward its interior.
Route according to normal clock-line requirements. No other signal should cross beneath the driver chip.
Because the clock signals around the driver chip are dense, their mutual interference and external interference are relatively strong. Keep unrelated circuits and signals away from them, and add shielding where possible.

Figure 53 | Schematic and PCB diagrams of the clock driver circuit