Common Signal Types in PCB Design: Digital, Analog, and Interface

Signal names on a schematic are more than labels. They identify the electrical role of a net, the devices it connects, and the constraints it places on layout. In board-level design, common signals are usually grouped as digital, analog, and interface signals. Digital groups include processor buses, memory interfaces, expansion buses, and PHY links. Analog groups include video, audio, and HDMI. Interface groups include serial ports, Ethernet, optical modules, USB, and JTAG. Recognizing these categories early helps with net assignment, connector selection, stackup planning, and routing rules such as single-ended versus differential pairs and impedance control.

The examples below use representative net names. The same signal functions can appear under different names depending on the device and vendor, so the function and timing relationship matter more than the exact label.

Highlights:

Digital signal groups such as CPU buses, SDRAM/DDR memory, PCI/PCI Express, and PHY interfaces have distinct naming, timing, and impedance requirements.
SDRAM is fully clock-synchronous and uses a 64-bit path with 3.3V LVTTL; DDR transfers on both clock edges, supports 2.5V/1.8V SSTL2, and requires 50Ω impedance control.
Interface signal families include analog audio/video and HDMI, serial/TDM, RJ45 Ethernet, optical modules, USB, and JTAG, each with defined pin and differential-pair conventions.

1. Common Signal Introduction

A signal is the physical representation of information moving between devices. In a PCB system, the same physical trace can carry a digital bit stream, an analog waveform, or a defined interface protocol. The signal type determines how the net should be treated during design: whether it needs a controlled impedance, whether it is single-ended or differential, whether it is clock-like or data-like, and whether it is sensitive to noise or is itself a noise source.

This section reviews the common signal groups found in processor, memory, peripheral, networking, multimedia, and test interfaces. It covers the function of each group, representative signal names, and the technical points that matter most when the signals are taken from schematic capture into PCB layout.

Digital Signals

CPU

The CPU is commonly called the processor. The system exchanges data among the processor, control chips, and memory through the data bus, address bus, and control bus.

Address bus: ADD* (for example, ADDR1).
Data bus: D* (for example, SDDATA0).
Control bus: read/write signals (for example, WE_N), chip-select signals (for example, SDCS0_N), address row/column select signals (for example, SDRAS_N), clock signals (for example, CLK), and clock-enable signals (for example, SDCKE).

The memory associated with the CPU includes SDRAM and higher-speed DDR memory.

SDRAM

SDRAM is a memory type widely used under the PC100 and PC133 specifications. It has a 64-bit data path, supports 3.3V LVTTL, and current products can reach 5ns. It exchanges data with the CPU at the same clock frequency, and its operating frequency is synchronized with the CPU external frequency. There is no delay or wait state, and SDRAM is fully synchronous with the clock.

DDR

DDR is a higher-speed memory than SDRAM and can reach 800 Mbps. It transfers data on both the rising and falling edges of the clock, so even at a 133MHz bus frequency the bandwidth can reach 2.128GB/s. Its address and other control interfaces are the same as those of SDRAM. It supports the 2.5V/1.8V SSTL2 standard, with impedance controlled at 50Ω ±10%. Data is transferred on clock edges at twice the SDRAM rate, and the DDR clock is differential.

PCI

The PCI bus is a high-speed 32/64-bit address/data bus used to interconnect control devices, peripheral interfaces, and processor/memory systems. PCI signal definitions include two parts: required signals in the left half and optional signals in the right half. The "#" suffix denotes an active-low signal.

Figure 2-1 | PCI Pin List; Figure 1 PCI signal layout diagram

Figure 1 | PCI Pin List; Figure 1 PCI signal layout diagram

Required pins cover data and address transfer, interface control, interrupt arbitration, and system functions.

Overall, reliable communication between the CPU, memory, and peripheral devices depends on proper signal assignment, impedance control, clock synchronization, and routing practices. SDRAM and DDR interfaces require careful attention to clock and data timing, while PCI and PCIe buses benefit from controlled routing and signal integrity management. For a more comprehensive overview of CPU subsystem and high-speed bus routing, including SDRAM, DDR, PCI, and PCIe design considerations, refer to the corresponding design guidelines.

PCI Express

PCI Express is the latest bus and interface standard. It was originally called "3GIO" and was renamed "PCI Express" after certification and release by PCI-SIG, the PCI Special Interest Group. Its main advantage is high data transfer rate, currently reaching more than 10GB/s, with considerable room for further development. PCI Express has several specifications, from 1X to 16X, to meet the needs of low-speed and high-speed devices now and for some time to come. The main chipsets supporting PCI Express are the Intel i915 and i925 series.

PHY

A PHY is a physical-layer data conversion chip in network protocols. It is mainly used between switch chips and network ports.

Figure 2 | PHY chip schematic

On the left side of the PHY are the data receive and transmit terminals:

Receive signal: RXDATA (0-7).
Receive clock: RXCLK.
Receive feedback signal: RXSYNC.
Transmit signal: TXDATA (0-7).
Transmit clock: TXCLK.
Transmit feedback signal: TXSYNC.

On the right side are differential data transmit and receive signals, such as (*RD-, *RD+) and (*TD-, *TD+).

Analog Signals

Audio and Video Signals

Video

Video signals include RGB signals, HSYNC, and VSYNC.

Audio

Audio signals include SPKR_L+/- and SPKR_R+/-.

HDMI

HDMI stands for High-Definition Multimedia Interface. An HDMI interface can provide up to 5Gbps of data bandwidth and can carry uncompressed audio and high-resolution video. It does not require digital-to-analog or analog-to-digital conversion before transmission, which helps preserve the highest audio and video quality. HDMI is pin-compatible with DVI but uses a different package. Compared with DVI, HDMI can transmit digital audio, adds HDCP support, and provides better optional DDC functions.

HDMI supports a 5Gbps data rate and a maximum transmission distance of 15 meters, enough for one 1080p video stream and one 8-channel audio signal. Because a 1080p video stream and an 8-channel audio signal require less than 4GB/s, HDMI has substantial margin. This allows one cable to connect a DVD player, a receiver, and a PRR. HDMI also supports EDID and DDC2B, so HDMI devices have plug-and-play behavior: the source and display automatically negotiate and select the most suitable video/audio format.

Interface Signals

Serial Port

Buffered Serial Port Signals

Receive clock: BCLKR0, BCLKR1; transmit clock: BCLKX0, BCLKX1.
Serial data receive: BDR0, BDR1; serial data transmit: BDX0, BDX1.
Synchronous receive: BFSR0, BFSR1; frame-sync transmit: BFSX0, BFSX1.

TDM Serial Port Signals

TDM receive clock: TCLKR; TDM transmit clock: TCLKX.
Serial data receive: TDR; serial data transmit: TDX.
Receive frame sync/address: TFSR/TADD; frame-sync transmit: TFSX/TFRM.

Ethernet Port

A single RJ45 Ethernet port consists of two differential pairs. An integrated Ethernet port consists of multiple pairs. For a single RJ45 port, an example signal group is RD+/- and TD+/-.

Optical Port

Optical module signals generally consist of two differential pairs and six control digital signals. The differential signals are RD+/- and TD+/-. The data signals are MOD_REF(0-2), LOS, TXFAULT, and TXDIS.

USB

USB, the Universal Serial Bus, uses a standard 4-pin plug. In a daisy-chain topology it can connect all peripherals, with support for up to 127 external devices. USB 1.1 can reach a transfer rate of 12 Mbps; USB 2.0 can reach 480 Mbps. Example signals are USBC_DP and USBC_DN.

JTAG

The JTAG test interface uses the following signals:

Test clock: TCK.
Test mode select: TMS.
Data input: TDI.
Data output: TDO.
Test port reset: TRST.
Emulation pins: EMU0; EMU1/OFF.

Related Reading: