Interface Circuit Layout and Routing Guide for PCB Designers

Interface circuits sit at the boundary between the PCB and the outside world. They carry a mixture of high-speed differential pairs, low-speed control lines, supply rails, and exposed connector pins that are directly reachable by the user. Because of that position, interface layout and routing decisions determine far more than signal quality alone: they set the board's EMC behaviour, its ability to survive ESD events, the continuity of its reference planes, and the quality of the power delivered to sensitive transceivers and modules.

The treatment of each interface differs according to its electrical nature. A UART pair is slow and single-ended, so its routing is dominated by placement and by the copper void beneath the connector. An Ethernet port combines an isolation transformer, impedance-controlled differential pairs, and a mandatory plane cut-out that separates primary from secondary. Optical modules demand short supply paths and careful handling of the shield can. USB requires controlled differential impedance plus EMC filtering. Audio and VGA interfaces are dominated by a 75 Ω impedance target, wide traces, and individual ground wrapping. This article works through these interface types in turn, giving the placement rules, routing rules, and plane-handling rules that apply to each.

Highlights:

Copper voiding under connectors and under isolation transformers is a structural requirement, not an optional refinement. It prevents coupling into the reference plane and preserves the primary-to-secondary barrier.
Each interface has its own impedance rule: Ethernet primary-side traces are not impedance controlled but are widened (typically 12 mil), while USB 2.0 is controlled to 90 Ω and audio/VGA are controlled to 75 Ω.
Decoupling and pull-up resistors belong as close as possible to the chip or connector pin they serve, and their pin escapes should be widened rather than left at minimum width.

Serial Port (UART) Circuit

A serial port is the simplest interface to route, but it still has a few placement and plane rules that are easy to overlook.

During placement, keep the resistors and capacitors as close as possible to the chip. During routing, widen the trace that connects to their pins rather than using the minimum width.
The TX and RX signal lines do not need to be routed as a differential pair. They are independent single-ended signals, and treating them as a pair provides no benefit.
The plane beneath the connector's signal pins is normally voided. If the serial port has a protection circuit, the plane beneath the protection circuit must be voided as well. If there is no protection circuit, only the area beneath the serial signal pins needs to be cut away.

The two cases are shown below: one PCB layout without protection circuitry, and one with protection circuitry added.

Figure 54 | PCB diagram of a serial port circuit without protection; layout and routing when the serial port has a protection circuit:

Figure 55 | PCB diagram of a serial port circuit with protection

Ethernet Port Circuit

The Ethernet interface is the most demanding of the connector-level interfaces, because it combines a transformer barrier, multiple differential pairs, and a mandatory plane separation.

The circuit consists of the RJ45 connector, an isolation transformer, the PHY, decoupling capacitors, and matching resistors. Some designs add a protection circuit and a Smith termination circuit.
Place the transformer as close as possible to the RJ45, keeping the trace length within 1000 mil. The distance to the PHY should also be as short as practicable.
Each center-tap PIN of the transformer requires its own decoupling capacitor (0.1 μF). On the primary side, the center taps are sometimes connected in an RC arrangement instead.
The Ethernet signal consists of several differential pairs. The traces on the primary side are not impedance controlled and should be made as wide as possible, typically 12 mil. The secondary-side differential pairs are routed according to normal differential-pair rules.
The signal trace that connects the transformer center tap to ground through a capacitor must be widened, typically to 20 mil.
All layers beneath the body of the transformer must be voided. Add an anti-etch region with a width of more than 100 mil.
No signal may be routed beneath the transformer, and signals must never cross between the primary and secondary sides.
For a conventional RJ45 connector, the copper beneath the connector body must be completely voided.

Figure 56 | PCB diagram of an Ethernet port circuit

Many Ethernet variants exist, including 100M Ethernet and 1000M Ethernet, the latter using four differential pairs. Some connectors integrate the transformer inside the RJ45 housing; in that case the same routing rules apply but the discrete transformer placement step disappears.

Figure 57 | PCB diagram of an Ethernet port circuit with an integrated transformer

Optical Port Circuit

The optical port is built from a 3.3V supply module, pull-up resistors, matching resistors, and the optical module itself. The module's mechanical position is normally fixed by the enclosure or the front panel, so the layout work concentrates on the components around it.

Because the module position is generally fixed, the pull-up resistors can be placed directly on the back side of the board near the pins. The supply circuit should be placed as close as possible, and the small decoupling capacitors must be placed close to the pins.
The module signals usually consist of two differential pairs plus six control signals, and they should be handled as high-speed signals.
The GND pins of the shell are normally connected to CGND, the protective ground.
Do not place non-ground vias underneath the shield can.

Figure 58 | Schematic and PCB diagram of an optical port circuit

Optical modules come in several package types according to transmission rate, but the transmission principle is essentially the same. One variant uses a +5V supply and a single control signal; other variants include versions with indicator LEDs and dual-channel versions.

Figure 59 | PCB diagram of a +5V power supply and dual-channel optical port

JTAG Circuit

The JTAG circuit consists of a test connector together with pull-up and pull-down resistors. It typically carries five test signal lines: TCK, TDI, TDO, TMS, and TRST#.

During placement, the pull-up and pull-down resistors should be placed close to the JTAG connector.
For a surface-mount JTAG connector, do not route vias inside the connector footprint.

Figure 60 | PCB diagram of a JTAG circuit

USB Interface Circuit

A USB connector generally has six pins: two mechanical mounting pins and four signal pins. The four signal pins are pin 1 for power, pin 2 for USB_N, pin 3 for USB_P, and pin 4 for GND.

The mechanical mounting pins should generally not be connected directly to digital ground. They are usually named CGND and can be tied to digital ground through a bridging capacitor.
USB_N and USB_P must be routed as a differential pair. For USB 2.0, the impedance is controlled to 90 Ω.
To address EMC, ferrite beads are sometimes added to the four signal pins for isolation, as shown in the layout below.

Figure 61 | PCB diagram of a USB circuit

Audio and Video Interface Circuits

Audio

Audio signal lines generally include SPKR_L+/-, SPKR_R+/-, AC_BITCLK, AC_SDATAOUT, AC_SYNC, and AC_SDATAIN, among which the AC'97 signals are digital.

The differential impedance is controlled to 75 Ω. Traces should be made as wide as possible, with 15 mil recommended. Keep these traces away from other signals and give them their own ground wrap.

VGA

VGA signal lines generally include R, G, B, HSYNC, and VSYNC. The impedance is controlled to 75 Ω.

During placement, the ferrite beads on the RGB lines should be placed as close as possible to the connector, so that the signal is decoupled before it is fed in. The RGB pull-up resistors can be placed at the chip end.

The RGB traces should be made as wide as possible, with approximately 15 mil generally recommended. The spacing between the three traces, and between them and other signals, should be as large as possible. The three RGB signals should each receive an individual ground wrap, and the three traces should be kept as equal in length as possible.

HSYNC and VSYNC are the horizontal and vertical sync signals. These two lines do not need to be routed as a differential pair. They should be kept away from other signals, given an individual ground wrap, and matched in length.

Figure 62 | Schematic of a VGA circuit