PCB Silkscreen Text Design and RF/AD-DA Layout Rules for Engineers

Silkscreen is the last thing a designer touches on a board and the first thing anyone sees on an assembled unit, which is why the rules governing it sit alongside the routing rules rather than after them. This article covers the practical requirements that link layout and post-processing on RF and mixed-signal boards: how the RF front end around the antenna and the RF processing chip should be routed, how analog and digital grounds are kept apart in A/D and D/A sections, and how silkscreen text, orientation, symbols, barcodes, and safety markings are specified once the layout is finished. Designers, layout engineers, and process engineers will find the trace, clearance, and font rules they need to keep a design both manufacturable and readable in production.

Highlights:

Keep RF traces on the surface layer, draw them as arcs at a minimum width of 15 mil with 50 Ω impedance, and clear traces and copper from every layer within at least 1 mm of the antenna projection area.
Never mix or interleave analog and digital routing; A/D and D/A traces stay off the shield ribs on the surface layer, and non-ground vias never land on a rib.
Silkscreen follows fixed font sizes and reading directions, never sits on pads or vias, and barcode placement keeps 5 mm from the board edge and 15 mm from the card handle.

RF Circuits

A typical mobile phone RF circuit is built from the antenna, an LC filter, an RF filter, the RF processing chip, and the resistors and capacitors that surround the chip. Some designs also add a test socket, a duplexer, or both.

Figure 65 | PCB diagram of mobile phone RF circuit

Antenna Section

The positions of the antenna and the filter are usually fixed by the mechanical design. What the layout engineer actually controls is the placement of the filter circuit itself. The entire RF path should read as one streamlined run. Traces should land directly on the capacitor or inductor pad with no corner at the pad, and should be drawn as arcs rather than angled segments: simple, short, and as direct as the available space allows.

When space runs out, one filter element is normally sacrificed. Given a choice between an inductor and a capacitor, the capacitor is the one to drop. C110 in the figure above, for example, can simply be moved aside. If a corner genuinely cannot be avoided, place the bend inside the pad.

Every layer must be cut back within at least 1 mm of the antenna projection area, with no traces and no copper pour of any kind. The RF trace itself is the obvious exception. The full RF trace should be at least 15 mil wide and held to a 50 Ω impedance. Satisfying both the impedance and the width requirement means adjusting the spacing between the trace and its reference plane. Within one trace width of the reference plane's projection, no other traces or copper are permitted.

RF traces must be routed on the surface layer; do not take them onto inner layers. Where a trace meets a shield rib, shielding can be traded away and the shield frame notched by the fabrication process. The area below C109 in the figure above is handled exactly this way.

RF Processing Chip Section

The resistors, capacitors, and inductors around the chip should sit close to its pins. Filter traces are widened and, wherever the geometry permits, turned into copper pours. The high-speed single-ended and differential lines leaving the chip follow 50 Ω single-ended and 100 Ω differential impedance. Use through vias in preference to layer changes, and change layers as little as possible. Surround the traces with ground, keep the adjacent layers grounded as well, and run differential pairs slightly wider than the calculated minimum. Power, of course, should pass through its decoupling capacitor before it reaches the chip.

Place ground vias evenly beneath the chip, and avoid routing nets belonging to other areas through that region.

Figure 66 | PCB diagram of mobile phone RF chip

Other Circuits

A/D and D/A Conversion Circuits

An A/D conversion circuit converts an analog signal into a digital one, while a D/A conversion circuit converts a digital signal into an analog one. Both usually have their own ground, defined as analog ground (AGND) and digital ground (DGND or GND).
During placement and routing, analog and digital must never be mixed or interleaved, and neither may cross over the other's reference plane.
A/D and D/A conversion circuits are normally fitted with a shield can, so traces and vias must not cross the shield ribs on the surface layer, and non-ground vias must not be placed on a rib.
Digital signals are generally calculated at 50 Ω impedance. Analog signals follow the chip datasheet, with 75 Ω and 50 Ω being the common values. Traces should be widened, and where necessary the spacing from the trace to the reference plane must be adjusted to meet both the impedance and the width requirement.

Post-Processing

Silkscreen Text

5.1.1 Font Size

Reference designators and pin numbers on ordinary resistors and capacitors use font size 3, with the following parameter values: Width: 30 mil; Height: 30 mil; Line Space: 0 mil; Photo Width: 6 mil.
Designators for locating connectors, key ICs, and other SMD components use font size 4, with the following parameter values: Width: 47 mil; Height: 63 mil; Line Space: 79 mil; Photo Width: 12 mil. Note that the Photo Width value must be changed here.

5.1.2 Direction

Surface layer: bottom to top, left to right, as shown in the figure below.

Figure 68 | Schematic diagram of text orientation on the top layer

Bottom layer: bottom to top, right to left, as shown in the figure below.

Figure 69 | Schematic diagram of text orientation on the bottom layer

Component Silkscreen Design Requirements

No silkscreen is permitted on solder mask openings or pads. Silkscreen over vias should be avoided as far as possible; characters such as 3, 6, and 8 in particular must not sit on a via.
Every component that is polarized or has an installation orientation must show that polarity and orientation in its silkscreen, and the marking must not be placed on a via.
If space limits force the removal of a component's silkscreen symbol, that symbol must still appear on the assembly drawing so the component can be located from it during assembly.

Board Name and Version Silkscreen

The board name and version are placed on the component side of the PCB. For double-sided assemblies, both sides of the board require the board name and version.
The board name silkscreen is sized for easy reading and must always be larger than the component designator silkscreen.

Barcode Silkscreen

The barcode silkscreen is placed horizontally or vertically.
The barcode must not cover pads or test points, and must not be covered by other components, so that the information stays readable.
Keep 5 mm from the board edge and 15 mm from the card handle.

Other Silkscreen

Optical fiducial numbers are uniformly designated "ID**".
Every RF PCB requires the silkscreen text "RF".
PCBs with fiber optic routing must show the fiber routing path on the PCB.
Boards that go through wave soldering must carry a clearly defined board travel direction.
If the assembly has a daughterboard or a heatsink, its outline must be marked in silkscreen at true size. Where the silkscreen would interfere with a component, indicate the outline with a broken silkscreen line.
The safety ESD marking uses the standard library symbol and is placed on the component side of the PCB wherever possible.
High-voltage marking.
Where a fuse is fitted, its designator and characteristics must be marked next to it in the following format: FX XXXV TX AH/XXXV. Here FX is the designator, XXXV is the supply condition, T is the fuse type (T for time-lag, F for fast-acting), X A is the rated current, H is the breaking characteristic (H for high-breaking, L for low-breaking; a -48 V supply may use a low-breaking fuse, and UL fuses carry no such marking), and XXXV is the fuse's working voltage. For example:

F1 230V T 4 AH/250V

This text must not be produced by editing the component designator silkscreen. Create a new silkscreen text item and place it aligned with the designator.

For -48 V and +27 V supplies there is no requirement on the fuse's time-lag or breaking characteristics, so in these two cases only the voltage and current need to be marked, for example: 4A/-48V.

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