PCB Routing Process and Power/Ground Handling Basics

Routing is the stage where component placement becomes a manufacturable, electrically functional PCB. It must satisfy mechanical constraints, design rules, fabrication and assembly requirements, and project-specific workflow requirements at the same time. Power and ground are treated as a separate design concern because their current-carrying capacity, return paths, protection, and filtering directly affect whether the system operates reliably. This part covers the basic routing principles and sequence, overall routing planning, rule setup, power and ground fanout, and the priority given to critical signals over other connections.

Highlights:

• Routing follows a fixed priority: rules first, critical signals first, and density first, starting from the most densely connected area on the board.
• Before full routing, BGA devices require fanout, and power/ground pins should be fanned out early with a length of no more than 200 mil and traces made as wide as possible.
• Layer planning should keep horizontal and vertical routing distinct, with adjacent layers routed perpendicular to each other and without overlap.

Routing

Basic Routing Principles

Routing must meet four groups of requirements:

1. Satisfy mechanical requirements, including checking and confirming the mechanical structure and keep-out areas.
2. Satisfy design rule requirements, including physical rules, electrical rules, DRC parameters, and option settings.
3. Satisfy process specification requirements, including DFM, DFT, soldering type, and the PCB manufacturer's processing capability.
4. Satisfy other relevant requirements, including customer design requirements, company process standards, and similar constraints.

Basic Routing Sequence

The routing sequence follows three priorities: rules first, critical signal lines first, and density first. In practice, routing starts from the most densely connected area on the board.

Overall Routing Planning

1. Confirm the feasibility of the routing plan established during placement.
2. Confirm how keep-out areas affect nearby routing channels.
3. Plan routing layers so that horizontal and vertical directions are clearly separated. Adjacent layers should route perpendicular to each other and should not overlap.
4. Before full routing, fan out BGA-packaged devices. Fanout for other package types is handled during detailed routing; see the FAN OUT section.
5. Power and ground pins should be fanned out before routing to reserve space. Power and ground fanout length should be ≤200 mil, and the traces wide should be made as wide as possible. See the FAN OUT section.

Design Rule Setup

1. Define keep-out areas.
2. Define physical and electrical rules completely and reasonably. When revising a board, confirm that the previous version's settings are still appropriate. DRC parameters and option settings must be correct.
3. Set vias, blind vias, and buried vias correctly, including the vias used under BGA packages and fine-pitch connectors.

Power and Ground Handling

Power is one of the core parts of the system, and its design quality directly affects whether the system can operate. In PCB design, power is mainly considered in terms of current-carrying capacity, power channels, protection, and filtering. See the Power and Ground Handling section.

Critical Signals

Give priority to the routing channels and routing topology of critical signals, including clocks, resets, and differential pairs. See the Critical Signal Handling section.

Other Signals

Without interfering with important signals, complete the connections in the optimal way allowed by the design rules.

Length Matching

Serpentine routing, commonly called length matching, is applied to satisfy signal timing requirements. When several signals in a parallel bus or a source-synchronous interface must arrive inside the same clock window, the physical lengths of their traces have to be equalized within a defined tolerance. Accordion-shaped detours add electrical length without moving the endpoints, which lets the designer align the arrival times of the whole group. The added segments should stay electrically short relative to the signal rise time, so that the detours do not introduce reflections or unexpected coupling that would cancel the timing benefit. Length matching is a timing measure, not a signal integrity measure, and it should not be used to compensate for a topology that is already wrong.

Power Path Design: Current Carrying Capacity and Plane Definition

Every chip consumes energy while it operates, and the channel that supplies that energy is the copper on the PCB. If the copper is undersized, the consequence is not a small efficiency loss: the trace heats up, the voltage delivered to the load sags, and in the worst case the trace fuses. Four factors determine how much current a piece of copper can actually carry: trace width, copper thickness, permitted temperature rise, and the layer on which the copper is placed. These four are not independent. Widening a trace on an inner layer with 1 oz copper can deliver less current than a narrower trace on an outer layer, and a wide trace whose local width is pinched by via clearances can behave like the narrowest point across its entire run. Each factor therefore has to be evaluated with the others in view.

1. Current Carrying Capacity

Trace Width

Trace width is the primary lever. For a discrete power trace it is simply the drawn width. When the power is delivered by a copper pour, the relevant dimension is the narrowest point of the pour, not its nominal or widest area. This point is often invisible in a casual review: a generous polygon can be pinched to a thin sliver where it squeezes between the antipads of vias belonging to other nets. The clearance width required by those vias must therefore be subtracted before the width is checked against the current requirement. The rule is to evaluate the pour at its bottleneck, because the bottleneck is what heats up first.

For long-distance routing, an additional 50% margin must be added to the calculated width. The purpose of this margin is straightforward: to guarantee that the PCB trace is never fused or burned through under abnormal conditions, and to absorb the resistance increase that comes with heating. A trace that is only just adequate at room temperature may become inadequate once the board interior warms up in an enclosure.

Suitable routing parameters for a given current can be determined with the PCBTEMP software tool, which takes the geometry and the thermal assumptions and returns the resulting current capability or temperature rise.

Figure 18 | PCBTEMP interface

The classical reference behind these calculations is the trace carrying capacity table derived from MIL-STD-275, reproduced below. It lists the maximum current in amperes for a given trace width, at three copper weights (1/2 oz, 1 oz and 2 oz) and three permitted temperature rises (10 °C, 20 °C and 30 °C). The table is a useful sanity check even when a calculator is available, because it makes the trade-offs between width, copper weight and allowable heating immediately visible.

Trace Carrying Capacity per MIL-STD-275

Reading across the rows shows why the width decision cannot be made in isolation. A 0.050-inch trace at 1 oz copper and a 10 °C rise is rated for 2.6 A, while a 0.100-inch trace under the same conditions reaches only 4.2 A. Doubling the copper width does not double the current capability, because the copper-to-air surface area available for heat removal grows more slowly than the cross-section. This is precisely why the design trade-off is usually resolved by increasing copper weight or changing layer rather than by continuing to widen the trace, and why the 50% long-distance margin is applied on top of a calculated value rather than instead of it.

Copper Thickness

Copper thickness refers to the copper weight of the layer on which the power trace runs. On common four-layer and six-layer stackups, inner layers that carry a mix of power and routing are built with 1 oz copper. This is a compromise driven by etch resolution and cost: thicker copper limits the minimum trace width and spacing that the fabricator can hold, so it is normally reserved for dedicated planes. If the current requirement calls for 2 oz or more, the recommended approach is to design the power plane and the ground plane onto the two opposite faces of a single core. Placing the heavy copper on the two sides of one core gives a tight power-ground loop, keeps the heavy copper adjacent so the pair behaves as a low-inductance sandwich, and avoids mixing heavy copper into the layers that carry fine-geometry routing.

Temperature Rise

Temperature rise is the permitted increase in the temperature of the whole PCB that results from the heating of the power traces. It is a budget, not a measurement: the designer chooses how much heating the board may tolerate, and then commits to a trace geometry that stays inside that budget. The choice depends on the ambient conditions the product will see, on the thermal sensitivity of nearby components, and on the glass transition temperature of the laminate. A generous rise allowance lets the copper be narrower, but it pushes the entire board closer to its thermal limits and shortens the operating life of every component on it. A tight rise allowance forces wider copper or heavier copper weight, consuming routing area.

Layer

The fourth factor is whether the power copper is routed on an outer layer or an inner layer. Outer layers sit in direct contact with the air and with the solder mask, so heat escapes far more readily; inner layers are encapsulated in laminate, which is a much poorer conductor of heat. For the same width, copper weight and permitted rise, an outer-layer trace therefore carries more current than an inner-layer trace. This is why a power net that is comfortably rated on the top layer can be marginal after it transitions to an inner layer through a via, and why the transition via itself must be checked as part of the same current path.

2. Power Channels

Be clear about every power path and about the overall power distribution of the board. In practice this means building an explicit map: which regulator feeds which rail, which rail feeds which device group, where the current enters the plane, and where it leaves the plane to reach the load. Each of these paths is a channel, and each channel has its own current, its own bottleneck and its own return path. A design that looks adequate at the schematic level can still fail because two high-current loads share a single narrow neck far from the regulator, or because the return current of one channel is forced to share a plane region with another. Mapping the channels before routing the copper makes the width and plane decisions a matter of arithmetic rather than guesswork, and it exposes shared bottlenecks that would otherwise only appear as thermal hot spots on the finished board.

3. Voltage Drop

Traces and copper pours are not ideal conductors; they have a finite resistance. When current flows through them, a voltage drop appears along the path, and the voltage that finally reaches the load is lower than the voltage at the regulator output. In many cases this drop can be ignored, particularly on short, wide, low-current paths where the resistance is a small fraction of an ohm. But wherever the voltage is tightly specified, the drop must be taken into account. The typical cases are core rails with narrow tolerance windows, analog references and ADC supplies whose accuracy depends directly on the rail, and any load that draws a large current through a long path. The drop scales with both current and length, so it is the combination of a long route and a heavy load that turns a negligible resistance into a specification violation. The fix is the same lever used for current capacity: more copper, either wider or thicker, or a shorter path, or both.

4. Power and Ground Splitting

The way the power and ground planes are split should be simple and reasonable, and the size of each split region must satisfy the current carrying capability of the rail it serves. A split that forces a heavy rail through a small island, or that leaves only a thin neck between a plane and its load, defeats the purpose of using a plane at all. The correct width of a split line is generally greater than 40 mil. For small regions the width has to be considered specifically, since the geometry of the split is dictated by the component footprint rather than by choice. The classic example is the split inside a BGA field, where the plane has to be threaded between a dense array of vias and pads. Recommended minimum split widths in that environment are: 1.27 mm BGA pitch ≥ 25 mil, 1.0 mm BGA pitch ≥ 20 mil, 0.8 mm BGA pitch ≥ 10 mil, and 0.5 mm BGA pitch ≥ 8 mil. The figure below shows the split line width inside a 0.5 mm BGA field and at its edge.

Figure 20 | Split line width inside and at the edge of a 0.5 mm BGA

The reasoning behind these graduated values is geometric. As the ball pitch shrinks, the space between adjacent via antipads in the BGA field shrinks with it, so the achievable split width falls. Accepting a narrower split is a compromise, and it must be paid for elsewhere, typically by making the neck as short as possible and by ensuring the current that crosses it is small.

5. The 20H Rule

The 20H rule governs how far the ground plane should extend beyond the power plane, and it is one of the cheapest edge-radiation controls available in a stackup. At the edge of the ground plane, including ground planes of different character, the ground plane should extend 20H beyond the power plane and the signal layers. Here H is the distance between the adjacent power plane and ground plane. The mechanism is simple: the electric field that fringes from the edge of the power plane is what radiates sideways out of the board. If the ground plane projects past that edge, the fringing field terminates on copper instead of on air, and the edge emission drops accordingly.

The same logic applies to routing. Critical signals should not be routed at the edge of the ground plane, because a trace running along a plane boundary loses its reference and its return current is forced to take a long detour, which both degrades signal integrity and increases emission. If a ring of ground is placed around the edge of the signal layer adjacent to the power plane, effectively acting as a guard rail, and that ring is stitched to the ground plane with vias at close spacing, the radiation is reduced further. A recommended stitching pitch for this ring is 200 mil. The figure below illustrates the 20H rule.

Figure 21 | 20H rule

Because the rule is expressed as a multiple of the plane separation, it scales automatically with the stackup: a thin dielectric between power and ground demands only a small inset, while a thick dielectric demands a larger one. This is one more reason the plane pair should be placed on adjacent layers of the same core, where H is small and the required inset is easy to accommodate within the board outline.

6. Voltage Difference Between Adjacent Split Regions

The voltage difference between adjacent split regions must not be too large. When two plane regions carrying very different potentials sit side by side with only a narrow isolation gap between them, the gap experiences a concentrated field, and the risk of creepage, arcing or coupling across the boundary rises. Where the difference is large, the width of the isolation line must be increased to reduce the potential gradient across the gap and to keep the two regions reliably separated. This is a geometric fix for an electrical problem: the same potential difference spread across a wider gap produces a lower field stress.

7. High-Voltage Rails and PGND

For high-voltage power and for PGND, the split lines should be widened beyond the values used for ordinary low-voltage rails. As a general recommendation, all holes, traces and copper pours should keep a spacing of at least 2 to 3 mm from high-voltage power and from PGND. This applies to vias belonging to other nets as much as to the high-voltage nets themselves, since a via barrel passing close to a high-voltage region is a potential breakdown path through the laminate. The spacing has to be checked in three dimensions, not only in the plane view: a hole on an inner layer is just as relevant as one on the surface, and the copper of an unrelated plane that happens to pass underneath a high-voltage region must also respect the clearance.

Taken together, these seven checks form one coherent review pass over the power delivery copper: verify the width and weight against the current and the permitted rise, confirm that every channel and its return path is accounted for, check the drop on the rails with tight tolerances, size and shape the splits to carry the current they serve, inset the power plane behind the ground plane, keep the potential difference across any gap within reason, and give high-voltage copper the extra clearance it requires. Each of these is inexpensive to fix in layout and expensive to discover after fabrication.

Related Reading: 

• PCB Layout Rules: Edge Clearance, Keep-Outs and Fiducial Marks
• Clock Circuit Layout and Routing for Crystals and Oscillators
• Interface Circuit Layout and Routing Guide for PCB Designers
• PCB Silkscreen Text Design and RF/AD-DA Layout Rules for Engineers
• CPU Subsystem and High-Speed Bus Routing: SDRAM, DDR, PCI, PCIe Rules
• Special Component Layout Rules for BGA, Press-Fit, and Thermal Parts