PCB Routing Safety: Trace Width, Clearance, and Thermal Rules

Routing is not only a matter of connecting nets. It directly affects fabrication yield, assembly reliability, signal behavior, and the ability of the board to survive mechanical and thermal stress. A route that looks correct in a netlist can still fail if it violates trace width limits, runs too close to the board edge, crosses a metal-housing contact area, or creates a solder mask and thermal condition that is difficult to manufacture.

This article covers the main routing safety requirements for PCB layout. It starts with trace width and clearance rules, then moves to distance requirements around board edges, metal components, and non-plated holes. It also reviews practical routing precautions, solder mask design, and thermal design details that affect SMT assembly and long-term reliability. The focus is on rules that can be checked during layout review and implemented directly in the CAD tool.

Highlights:

Use trace widths and spacings that match the PCB fabrication process: outer layer ≥6mil/7mil, inner layer ≥5mil/6mil, and a minimum usable width/spacing of 4mil/5mil. Keep trace width within the component pad width.
Keep routing, vias, and copper pour more than 20mil from the board edge. Keep signal traces at least 20mil from the edge, with 40mil or more recommended. Provide a 1.5mm top-layer routing keepout around metal component contact areas.
Maintain solder mask bridges, control via and test-hole openings, plug BGA vias, and use symmetrical thermal connections to reduce tombstoning, solder wicking, and poor solder joint formation.

Routing Safety

Routing safety begins with the physical limits of the fabrication and assembly processes. Trace width, spacing, distances to board features, and keepout zones must all be defined before detailed routing starts. If these rules are applied late, they often force rerouting around connectors, mounting holes, metal hardware, and thermal pads.

Trace Width Requirements

Route with trace widths and spacings that meet PCB fabrication process requirements. The recommended trace width/spacing is outer layer ≥6mil/7mil and inner layer ≥5mil/6mil. The minimum usable trace width/spacing is 4mil/5mil.
Trace width must not exceed the width of the component pad to which it connects, as shown in the following figure.

Figure 23 | Trace width does not exceed the component pad width

The trace width rule is not only about current carrying capacity. A trace that is wider than its pad creates an abrupt geometry change at the pad interface, can reduce the effective solder mask clearance, and may make the pad difficult to manufacture consistently. The trace should enter and leave the pad with a controlled width so that the pad remains the dominant feature.

Clearance Requirements

Clearance rules protect the board edge, prevent solder bridging, and avoid accidental contact with metal hardware. They also define the keepout zones around holes. The following requirements apply to routing, vias, copper pour, pads, and metal components that contact the PCB.

Keep routing, vias, and copper pour more than 20mil from the board edge.
The distance from an outer-layer trace and pad must satisfy a minimum of 2mil from the trace to the edge of the pad solder mask opening.
Trace-to-pad clearance: the outer-layer trace-to-pad clearance must match the inner-layer trace-to-annular-ring clearance requirement.
Do not route in the same-layer area where a metal housing directly contacts the PCB. Examples include heat sinks, power modules, metal handle strips, horizontally mounted voltage regulators, crystals, and ferrite inductors.
The area extending 1.5mm outward from the contact region between the component metal shell and the PCB is a top-layer routing keepout.

When a metal housing, heat sink, or shield directly contacts the PCB, any trace in that same-layer contact area can be scratched through the solder mask or shorted to the metal. Extending the keepout 1.5mm outward from the contact area provides margin for assembly tolerance, coating thickness, and placement variation. This is especially important for components that are screwed, clamped, or pressed against the board.

Non-Plated Hole Clearance

For non-plated holes, the minimum trace clearance depends on the hole diameter and whether the hole is a mounting hole. The clearance is measured from the hole edge to the nearest trace edge. Mounting holes follow the dedicated mounting-hole design rules. Non-mounting holes use the values below.

NPTH diameter	Hole type	Minimum trace distance from hole edge
NPTH diameter <80mil	Mounting hole	See mounting-hole design
NPTH diameter <80mil	Non-mounting hole	8mil
80mil < NPTH diameter < 120mil	Mounting hole	See mounting-hole design
80mil < NPTH diameter < 120mil	Non-mounting hole	12mil
NPTH diameter >120mil	Mounting hole	See mounting-hole design
NPTH diameter >120mil	Non-mounting hole	16mil

Mounting-Hole Keepout Requirements

Mounting holes carry mechanical load and may be close to screws, washers, or metal standoffs. The keepout diameter on the outer layer and the inner-layer distances protect both the hole wall and nearby copper. The required dimensions are summarized below.

Type	Diameter specification (mm)	Minimum top-layer keepout diameter (mm)	Minimum inner-layer distance: plated hole to trace edge (mm)	Minimum inner-layer distance: power/ground copper to NPTH edge (mm)
Screw hole	2	7.1	0.4	0.63
Screw hole	2.5	7.6	0.4	0.63
Screw hole	3	8.6	0.4	0.63
Screw hole	4	10.6	0.4	0.63
Screw hole	5	12	0.4	0.63
Rivet hole	4	7.6	0.4	0.63
Rivet hole	2.8	6	0.4	0.63

Routing Design Considerations

After the width and clearance limits are defined, the routing itself must be checked for signal integrity, manufacturability, solder mask quality, and thermal behavior. The following rules apply during interactive routing and post-route review.

General Routing Rules

Keep signal traces away from the board edge by at least 20mil, with 40mil or more recommended. In practice, this clearance is usually governed by the anti-etch clearance.
Components fixed by the mechanical structure must not be moved.
Plan layers so that routing is predominantly horizontal and vertical. Adjacent layers should not route in parallel. If parallel routing is unavoidable, keep the parallel length ≤1000mil.
Use a ground plane as the reference for all signal traces wherever possible. Important signals, such as clock signals, must use a ground plane reference.
Except for short interconnect traces and short fanout traces, route signal lines on inner layers.
Define clear routing zones. Signals should not cross between zones. Keep high-interference signals away from sensitive signals, and separate digital and analog routing.
Avoid unnecessary trace stubs, extra vias, and isolated copper islands.
The layout must be free of DRC errors and same-name net errors.
Do not use acute-angle routing. All signal traces should use 45-degree or arc routing unless a special case requires otherwise.
Do not place pads directly on through holes or mechanical blind holes.
Do not place vias in areas used for SMD adhesive dispensing or printing, such as the PCB area under CHIP and SOP components when adhesive dispensing or printing is used.
Ground heat sinks and heat spreaders as required.

Solder Mask Design

Solder mask is part of the electrical and assembly process, not just a cosmetic layer. The following rules prevent solder wicking, bridging, exposed copper in the wrong places, and mask openings that interfere with assembly.

Retain a solder mask bridge between adjacent SMD pads, between an SMD pad and a THD hole, between an SMD pad and a via, and between via and via. The minimum green oil bridge width is 4mil. This prevents solder from flowing away through the via or causing a short circuit.
Copper pour used for heat dissipation should have a solder mask opening.
For ordinary vias, the solder mask opening on both sides is the hole diameter +5mil.
For test holes, the front-side solder mask opening is the hole diameter +5mil, and the back-side opening is the pad diameter +8mil.
Provide a solder mask opening in the keepout area on both sides of mounting holes.
For non-plated locating holes, the solder mask opening on both sides is 6mil larger than the hole diameter.
Vias in the BGA area must be plugged with green oil. No solder mask opening is made on either side.
Traces generally require green oil coverage. RF PCBs may expose traces for impedance control.
The gold finger solder mask opening should be a full window. The top edge should align with the upper end of the gold fingers, and the bottom edge should extend beyond the board edge below the gold fingers.

Thermal Design

Thermal behavior during reflow and in operation depends on pad geometry, copper connection, and via placement. The following rules address both assembly yield and long-term reliability.

The heat capacity at the two ends of an SMT pad should be as equal as possible. The trace width should generally not exceed two-thirds of the pad width. Otherwise, the component is prone to tombstoning during reflow.
When a pad must connect to a large copper area, connect the pad to the copper with star-shaped or cross-shaped spokes. This increases thermal resistance between the pad and the copper and prevents heat from conducting away too quickly during processing, which can affect solder joint reliability.
For plated through-hole pads that carry high current, add vias beside the pad to ensure the electrical connection.
Avoid routing other traces through power devices and high-heat devices.
For a horizontally mounted voltage regulator module, add top-layer copper under the module. Reserve a heat-sink mounting location if necessary, and consider whether a solder mask opening is required.
Connect the LDO thermal pad to ground or to the relevant power rail according to the actual circuit. If this is not confirmed, do not ground the pad casually. Note that this pad is sometimes a power pin.
Make the traces connected to the pads as symmetrical as possible, as shown in the following figure.

Figure 24 | Symmetry of traces at both ends of a discrete component

Symmetry in pad connections helps balance heat flow during soldering. When one side of a discrete component is connected to a large copper area and the other side is not, the two terminals reach reflow temperature at different rates. The result can be uneven wetting, a shifted component, or a tombstone defect. The routing and copper connection should be reviewed together, not as separate layout tasks.

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