Surface Microstrip vs. Inner-Layer Stripline Routing

Routing-layer selection is sometimes treated as a late-stage layout preference, but for sensitive and high-speed nets it is a design decision that changes the electrical model of the interconnect. A clock, a high-frequency signal, a high-speed signal, a small-amplitude signal, or a weak signal all depend on the layer assignment chosen for its route. High-speed buses follow the same rule: the layer decision cannot be ignored simply because many signals are being routed together. The physical layer determines whether the trace behaves as a microstrip or a stripline, and that choice changes the propagation delay, characteristic impedance, and intrinsic capacitance and inductance relationships used during design.

This article compares surface routing with inner-layer routing. It defines microstrip and stripline, presents the first-order relationships for propagation delay and intrinsic line parameters, and shows why the same dielectric material can produce different timing depending on the layer used. The goal is to make the routing-layer decision explicit, so that layout, timing, and impedance calculations are based on the actual transmission-line cross-section rather than on an assumed one.

Highlights:

Layer choice matters for clocks, high-frequency and high-speed signals, small and weak signals, and high-speed buses because it determines which transmission-line model applies.
Microstrip is an outer-layer trace adjacent to a reference plane; stripline is an inner-layer trace between two reference planes.
For FR-4, the relationships give a propagation delay of 142.2 ps/inch for microstrip and 180.3 ps/inch for stripline, so surface and inner-layer routing do not have the same timing behavior.

2 Preferred Routing Layers

For clocks, high-frequency signals, high-speed signals, small-amplitude signals, and weak signals, selecting an appropriate routing layer is important. The same is true for high-speed buses. In these cases, the routing layer is not merely a physical location on the board. It is part of the electrical definition of the net. A trace on an outer layer and a trace on an inner layer can have different reference-plane arrangements, different field distributions, and therefore different delay and impedance relationships. If the layer assignment is left implicit, the subsequent calculations may describe a transmission line that is not the one actually built.

The practical problem is not that one layer type is always better than the other. The problem is that the layer type must be known and used consistently. A high-speed bus makes this especially visible because the layer decision applies across a group of related nets, so an assumption made for one trace is repeated across the bus. For a clock or a weak signal, the same decision affects the delay and the intrinsic line parameters that describe how the trace stores and transfers energy. The comparison between surface and inner routing therefore belongs at the beginning of the layer-selection process, not at the end of layout.

The first comparison is between surface traces and inner-layer traces, that is, between microstrip and stripline. Microstrip and stripline are summarized here for quick reference before their equations and FR-4 values are compared.

Surface and Inner-Layer Routing Compared

A surface trace and an inner-layer trace are both PCB interconnects, but they do not sit in the same electromagnetic environment. A microstrip is a trace on an outer layer with an adjacent reference plane. A stripline is a trace between two reference planes. The difference in reference-plane count and in the surrounding dielectric and conductor geometry is what separates the two transmission-line families. The comparison is therefore not a matter of naming convention. It determines which physical variables enter the delay and impedance equations, and it determines the numerical values that result for a given dielectric material.

Characteristic	Microstrip	Stripline
Physical placement	Outer-layer trace	Inner-layer trace
Reference planes	One adjacent reference plane	Two reference planes, one on each side
Propagation delay	85√(0.475ε_r + 0.67) ps/inch	85√ε_r ps/inch, or 1.017√ε_r ns/ft
FR-4 propagation delay	142.2 ps/inch	180.3 ps/inch
Intrinsic capacitance	C₀ = 1000 × t_PD / Z₀ (pF/ft)	C₀ = 1000 × t_PD / Z₀ (pF/ft)
Intrinsic inductance	L₀ = Z₀² C₀ (pH/ft)	L₀ = Z₀² C₀ (pH/ft)

The table shows the common structure behind the two line types. Both use propagation delay, characteristic impedance, and intrinsic capacitance and inductance per unit length. The numerical result, however, depends on the layer and on the cross-section. For the same FR-4 dielectric, the microstrip delay is 142.2 ps/inch, while the stripline delay is 180.3 ps/inch. That difference is large enough to matter in timing budgets and in layer-assignment decisions for high-speed nets.

Microstrip

Definition: A microstrip is a surface routing trace adjacent to a reference plane.

For microstrip, the propagation delay is expressed as a function of the relative permittivity of the dielectric:

Propagation delay: t_PD = 85√(0.475ε_r + 0.67) ps/inch

The intrinsic capacitance and intrinsic inductance follow from the delay and the characteristic impedance:

Intrinsic capacitance: C₀ = 1000 × t_PD / Z₀ (pF/ft)
Intrinsic inductance: L₀ = Z₀² C₀ (pH/ft)

For the commonly used FR-4 dielectric material, the microstrip propagation delay simplifies to:

FR-4 microstrip propagation delay: t_PD = 142.2 ps/inch

This value is a direct consequence of the microstrip cross-section and the FR-4 permittivity. It is the number to use when the trace is on an outer layer and is referenced to an adjacent plane. The same net routed as a stripline will not have this delay, even if the dielectric material is unchanged.

Stripline

Definition: A stripline is a PCB routing trace between two reference planes.

For stripline, the characteristic impedance is related to the dielectric permittivity and the cross-sectional geometry:

Characteristic impedance: Z₀ = (60 / √ε_r) ln[4h / (0.67πw(0.8 + t/w))] Ω

Here, h represents the dielectric height, w represents the trace width, and t represents the trace thickness. The propagation delay is:

Propagation delay: t_PD = 1.017√ε_r ns/ft, or t_PD = 85√ε_r ps/inch

The intrinsic capacitance and intrinsic inductance use the same forms as for microstrip:

For the commonly used FR-4 dielectric material, the stripline propagation delay simplifies to:

FR-4 stripline propagation delay: t_PD = 180.3 ps/inch

The contrast with the microstrip value is significant. At 142.2 ps/inch for microstrip and 180.3 ps/inch for stripline, the difference is about 38.1 ps/inch in FR-4. Over a 10-inch route, that difference accumulates to roughly 381 ps. For a clock, a high-speed bus, or any net with a tight timing relationship, this is not a secondary effect. It is a direct result of choosing a surface layer or an inner layer.

The stripline equations also make the geometry dependence explicit. The characteristic impedance depends on the dielectric height, trace width, and trace thickness, while the propagation delay depends on the dielectric permittivity. Once the line is placed between two reference planes, the design must use the stripline relationships rather than the microstrip relationships. The same principle applies in reverse: a surface trace must be treated as a microstrip, with its own delay formula and its own FR-4 value.

This is the practical answer to the layer-selection problem. The designer should not ask only whether a layer is available or convenient. The designer should ask which transmission-line model the route will follow, what delay that model produces, and whether that delay is acceptable for the signal class. For high-speed buses, the answer should be consistent across the bus. For clocks, high-frequency signals, small signals, and weak signals, the answer should be established before the route is used to support timing or impedance calculations.

Microstrip Topology

The microstrip topology is defined by a signal trace on an outer layer with an adjacent reference plane. That physical arrangement is the basis for the microstrip delay and intrinsic-element relationships given above. The trace and the reference plane form the transmission-line cross-section, and the dielectric permittivity and geometry determine the resulting electrical values. When the layer assignment changes from surface to inner layer, the topology changes from microstrip to stripline, and the equations and FR-4 delay values must change with it.

Definition

A microstrip is formed by an outer trace layer on a PCB that is adjacent to a solid reference plane, separated from it by a dielectric material. The trace and the plane beneath it together form the transmission line, with the dielectric setting the characteristic impedance and the propagation characteristics of the line. Because the trace runs on the surface, it stays visible, which makes it easy to inspect, probe, and debug.

Advantages

Routing a signal as a microstrip on an outer layer provides two main benefits:

It allows faster propagation of a signal down the transmission line.
It provides less capacitive coupling and a lower unloaded propagation delay for the signal of interest.

Disadvantages

The open surface geometry that gives the microstrip its speed also creates a drawback:

It allows RF energy within the transmission line to propagate into free space or into the surrounding environment.

Stripline Topology

A stripline is a routing layer located between two solid planes, with a dielectric material separating the routing layer from the reference planes. The trace is enclosed by dielectric and plane on both sides, and this geometry produces several distinct behaviors:

It provides better noise immunity for RF emissions.
It slows the propagation of the signal within the transmission line. This only matters for extra high-speed circuits that have critical signaling requirements.
Capacitive coupling increases, which affects signal integrity and impedance control.
It provides complete shielding of RF energy generated from internal traces, preventing that energy from radiating to the external environment.
RF energy can still be created by component pins and packaging material, which are always located on the outer layers of the PCB assembly.

Microstrip and Stripline: A Direct Comparison

The two topologies differ in propagation delay, intrinsic capacitance, radiation, and accessibility:

The transmission delay of a microstrip is lower than that of a stripline (38.1 ps/inch).
For a given characteristic impedance, the intrinsic capacitance of a microstrip is smaller than that of a stripline.
A microstrip sits on the surface layer and radiates directly to the outside. A stripline sits on an inner layer and is shielded by the reference planes.
A microstrip is visible, which makes debugging convenient. A stripline is not visible, which makes debugging inconvenient.

Considering the shielding effect of the reference planes, existing test data show that the radiation from a microstrip is approximately 20 dB greater than that from a stripline.

Radiation and EMI Propagation

EMI couples to the outside world mainly through two paths: conduction and radiation. Both paths apply to transmission lines as well.

For a stripline, because it is sandwiched between two planes, its radiation path is well controlled. Its main external propagation path is therefore conduction. The key concerns become the power and ground ripple during power delivery, together with crosstalk to adjacent traces.

For a microstrip, the conduction path that a stripline has is still present, but the trace's own external radiation becomes critical to the EMC budget. Not every surface trace deserves the same level of attention. The types of signals that radiate most are discussed in the section on special signal handling. The near-field field-strength measurement results for one particular board are shown below:

As the figure shows, the external radiation from critical routing, a considerable portion of which is the data bus, is about 18 dB higher than the radiation from other traces.

Traces That Require Special Attention

From an EMC design perspective, two categories of routing need to be watched:

Strongly radiating signal lines, such as high-frequency and high-speed signals and especially clock lines, because of their external radiation.
Small and weak signals, along with signals such as reset that are very sensitive to external interference, because they are easily disturbed.

Both categories must be given full attention. Where conditions permit, route them on inner layers, increase their spacing from other traces, and add shielding ground traces for isolation where necessary. Which specific traces require this treatment is examined in more depth in the section on special signal handling.

A Note on Device Radiation

In general, the radiation of the device itself has already been taken into account during device design. It is assumed that the device meets its own radiation specification, and special devices come with their own shielding or other countermeasures. The focus here is therefore on the external radiation of the transmission line.

Practical Design Observations

Comparing similar PCBs from Siemens and Motorola reveals that they place very little routing on the surface layer. Their use of buried and blind vias preserves the integrity of the reference planes and reinforces the shielding effectiveness of the surface layer. Our own boards, by contrast, still route quite heavily on the surface, sometimes at a density even higher than that of the inner layers. This stems partly from cost considerations and partly from insufficient attention to board-level EMI radiation. Given the current PCB design cycle, it is also difficult for an ordinary CAD engineer to develop a comprehensive understanding of all the signals on a board.

The EMC test results for the Brazilian project on switching products show that some clock and other signal lines with relatively low frequency and rate radiate far more than other signal lines. From an EMC perspective, critical signals, especially clock signals, should be routed on inner layers first. Other signals, especially those whose radiation behavior is not yet clear, should be routed on inner layers as much as possible. For boards whose overall radiation baseline is high, surface shielding or an added board-level shield can be considered.

Routing Layer Priority

Routing-layer priority is not simply a matter of choosing a layer number. It is a design decision that combines reference-plane integrity, layer adjacency, EMC behavior, routing congestion, and manufacturing constraints. A layer that is preferred for ordinary traces may be a poor choice for a critical net if its reference plane is split or if an adjacent signal layer carries long parallel traces. The following general principles provide a starting point for layer selection.

Based on available data and practical experience, preferred routing layers should be selected according to these principles:

Give priority to inner layers.
Give priority to a layer with no adjacent routing layer, or, when an adjacent routing layer exists, to a layer whose corresponding region has no traces on that adjacent layer.
For inner-layer routing, apply the priority relationship L > L > L; that is, give priority to the layer intended to serve as the reference plane.
Use routing layers that ensure critical traces do not cross split regions.

These principles need explanation. Inner layers are generally preferred because they are better shielded from the outside environment and can be placed close to solid reference planes. A layer with no adjacent routing layer avoids broadside coupling; if an adjacent routing layer cannot be avoided, the preferred layer is the one whose adjacent layer has no traces in the corresponding area. The inner-layer priority L > L > L reflects the fact that not all inner layers have the same reference conditions. The layer that is best suited to act as a reference plane should be selected first. Finally, a critical trace must not cross a split in its reference plane. A split breaks the return-current path, increases loop area, and can degrade signal integrity and EMC performance.

It must be emphasized that PCB design requires a comprehensive trade-off among function, cost, EMC, manufacturability, and appearance. There is no immutable rule for selecting routing layers. The recommendations above are general guidance only, for reference during PCB design. The value of a CAD engineer lies precisely in balancing these factors and finding the best compromise.

For example, the ten-layer board stack-up options discussed in the layout section are summarized in the following table. In the table, S denotes a signal layer, G denotes a ground plane, and P denotes a power plane. The numbers 1 through 10 are the physical layer positions from top to bottom.

Scheme	Power	Ground	Signal	1	2	3	4	5	6	7	8	9	10
1	1	3	6	S1	G1	S2	S3	G2	P	S4	S5	G3	S6
2	1	4	5	S1	G1	S2	G2	S3	G3	P	S4	G4	S5
3	2	3	5	S1	G1	S2	P1	S3	G2	P2	S4	G3	S5
4	2	4	4	S1	G1	S2	G3	P1	P2	G3	S3	G4	S4

The four schemes differ in the number of power and ground planes and in the placement of the signal layers. These differences change the reference environment of each signal layer, which is why the same ten-layer board can produce different routing priorities. The rankings below are based on the idealized assumption that the reference planes are continuous and that adjacent signal layers are not carrying long parallel traces. In practice, the ranking is a starting point for assigning critical nets, not a substitute for checking the actual return path. A layer ranked lower can still be used for non-critical or short traces.

In Scheme 1, S2 and S3 are inner layers and form a signal-layer pair between two ground planes, G1 and G2. When routing critical signals, S2 and S3 should therefore be considered first. At the same time, long parallel traces between these layers must be avoided for critical nets, because broadside coupling between adjacent signal layers can degrade signal quality. S4 and S5 are basically the same as S2 and S3, but the pair is located between the power plane and G3: S4 faces the power plane and S5 faces G3. The EMC environment between a power plane and a ground plane is inferior to that between two ground planes, so S4 and S5 have lower priority than S2 and S3. Within this pair, S5 uses the lower-impedance G3 as its reference plane, so its priority is slightly higher than that of S4. S1 and S6 are both surface layers. In general, the top layer has a higher device pin density than the bottom layer, so between the two surface layers S6 is preferred. The resulting priority for Scheme 1 is S2 = S3 > S5 > S4 > S6 > S1.

This ranking does not consider power/ground plane splits. In actual design, split regions may change the result, so the routing layer should be checked against the plane geometry before critical traces are assigned.

Using the same analysis, Scheme 2 ranks its signal layers as S2 = S3 > S4 > S5 > S1. Scheme 2 has one power plane and four ground planes. The signal layers are S1 at layer 1, S2 at layer 3, S3 at layer 5, S4 at layer 8, and S5 at layer 10. S2 is adjacent to G1 and G2; S3 is adjacent to G2 and G3. Each of these inner signal layers therefore has a ground plane on both sides, which is the strongest reference condition in this stack-up. S4 is adjacent to P at layer 7 and G4 at layer 9, so it has a power/ground reference pair rather than a ground/ground pair. S5 is the bottom surface layer and is referenced to G4. S1 is the top surface layer and is referenced to G1. Because S2 and S3 have the best reference environment, they share the highest priority. S4 comes next because it is still an inner layer with a nearby reference plane, even though one side is a power plane. Between the two surface layers, S5 is preferred over S1 because the top layer usually carries more components and has higher pin density.

In Scheme 3, S2, S3, and S4 are all inner signal layers between a power plane and a ground plane. Scheme 3 has two power planes and three ground planes. S2 is adjacent to G1 and P1; S3 is adjacent to P1 and G2; S4 is adjacent to P2 and G3. Thus all three inner signal layers are bounded by a power plane and a ground plane. Their reference-plane quality is similar, so they are ranked equally. S5 is the bottom surface layer and is referenced to G3. S1 is the top surface layer and is referenced to G1. The surface-layer comparison again favors S5 over S1. The ranking for Scheme 3 is therefore S2 = S3 = S4 > S5 > S1.

In Scheme 4, S2 and S3 are inner layers bounded by ground planes, and S4 is the bottom surface layer with a direct G4 reference. Scheme 4 has two power planes and four ground planes. S2 is adjacent to G1 and G3, so it is bounded by ground planes. S3 is adjacent to G3 and G4, so it is also bounded by ground planes. S4 is the bottom surface layer and is referenced to G4. S1 is the top surface layer and is referenced to G1. In this arrangement, the two inner signal layers have the strongest reference conditions, and the bottom surface layer is grouped with them under the simplified comparison used for this stack-up. S1 remains the least preferred layer. The ranking for Scheme 4 is S2 = S3 = S4 > S1.

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