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Impedance Control Basics: Characteristic Impedance Explained

Author : Alex Chen | PCB Design & High-Speed Engineering Specialist

November 13, 2026


Impedance control is a core requirement in high-speed PCB design. Every segment of trace on a board has a specific impedance value, and as data rates rise, a PCB trace no longer behaves like a simple short connection but like a transmission line whose voltage and current differ from point to point at the same instant. This article explains the physical meaning of input impedance and characteristic impedance, builds the transmission line model, presents the telegraph equations, and defines the general solution together with the propagation constant, characteristic impedance, reflection coefficient, and traveling wave coefficient. These definitions form the foundation for understanding how stack-up, trace geometry, and manufacturing tolerances affect the impedance of a finished board.

Highlights:

  • In lumped circuits, input impedance (U/i) describes a one-port network, but once a trace behaves as a transmission line the voltage and current vary along its length, and distributed parameters must replace lumped parameters.
  • The telegraph equations describe a lossy transmission line, and their general solution shows that the voltage and current at any point are the superposition of an incident wave and a reflected wave.
  • Characteristic impedance, reflection coefficient, and traveling wave coefficient are all defined through incident and reflected waves and remain valid at every point along the line, not only at its two ends.

3 Impedance Control

3.1 Physical Meaning of Characteristic Impedance

Input Impedance

In lumped circuits, input impedance is a frequently used term. Its physical meaning is the ratio of the voltage to the current seen looking into a one-port network, as shown below.

Figure 1 | Input impedance

Figure 1 | Input impedance

Input impedance: Zin = U / i

Characteristic Impedance

For a PCB, every segment of trace carries a specific impedance value. Trace inductance is one of the important contributors to RF radiation from a board. Even the lead inductance between a chip's silicon die and its mounting pad can develop a considerable RF potential, and long, thin traces are especially prone to large lead inductance. When an RF voltage is applied across a segment of impedance, a corresponding RF current flows and electromagnetic interference can result.

As signal transmission rates increase, PCB traces exhibit transmission-line behavior. On a connection that is treated as a short line in lumped analysis, the current and voltage at different positions at the same instant are no longer equal, so lumped parameters cannot represent the behavior and distributed parameters must be used instead. The transmission line model is shown below.

Figure 2 | Transmission line model

Figure 2 | Transmission line model

We can now solve the physical equations for this transmission-line model. The properties of a transmission line are described by the telegraph equations:

dU/dz = -(R + jωL) I

dI/dz = -(G + jωC) U    (1)

The general solution of the telegraph equations is given by (2). It contains two key quantities: the propagation constant (3) and the characteristic impedance (4).

From the general solution it is clear that the voltage and current at any point on the transmission line are the superposition of an incident wave and a reflected wave. The input impedance at any point on the line is therefore a function of time, position, and the termination, so using input impedance to study the line no longer serves a useful purpose. This is why the concepts of characteristic impedance, traveling wave coefficient, and reflection coefficient are introduced. Note that the reflection coefficient and the traveling wave coefficient are not limited to the two ends of the line; they are meaningful at any point along it.

Characteristic impedance is a central concept in transmission line theory. It is the equivalent of the distributed capacitance and inductance along the line, and its physical meaning is the ratio of incident-wave voltage to current, or equivalently the ratio of reflected-wave voltage to current. Solving the telegraph equations gives the characteristic impedance in equation (4). Because R and G are relatively small, it can be simplified to:

Z0 ≈ √(L/C)    (5)

The reflection coefficient is the ratio of the reflected-wave voltage (or current) to the incident-wave voltage (or current) at a given point on the line:

Γ = Ureflected / Uincident    (6)

The traveling wave coefficient is the ratio of the minimum voltage (or current) to the maximum voltage (or current) at a given point on the line. Both quantities are closely related to characteristic impedance.

Even-Mode Impedance, Odd-Mode Impedance, and Differential Impedance

When two transmission lines are routed close together, coupling exists between them. This coupling changes the characteristic impedance of each line and introduces the concept of an effective characteristic impedance. The effect can first be understood from the voltage and current relationships on a coupled pair. For the two coupled lines shown below, the voltage on each line depends not only on its own current but also on the current in the other line.

Figure 3 | Schematic diagram of transmission line coupling

Figure 3 | Schematic diagram of transmission line coupling

The voltage relations can be written as follows:

(7)   V1 = Z11 × i1 + Z11 × k × i2

(8)   V2 = Z22 × i2 + Z22 × k × i1

In these equations, k is the coupling coefficient. Z11 and Z22 are the self impedances of the two lines. When the two lines are identical, Z0 = Z11 = Z22. For a differential signal, the currents are equal and opposite, so i1 = -i2. Substituting this condition into the voltage equations gives:

(9)   V1 = Z0 × (1 - k) × i1

(10)   V2 = -Z0 × (1 - k) × i1

This result defines the odd-mode impedance Zodd. The odd-mode impedance is the effective characteristic impedance of a single transmission line in a coupled pair when a differential signal propagates along the pair. It is given by:

(11)   Zodd = Z0 × (1 - k)

To overcome reflection, the termination resistor added to each differential line should be the odd-mode impedance Zodd, not the isolated-line characteristic impedance Z0. In many differential signal applications, a single resistor of value 2Zodd is connected across the differential pair to avoid introducing noise from ground. This resistor is the differential resistor, and its value should be twice the odd-mode impedance:

(12)   Zdiff = 2 × Zodd

The differential impedance is therefore twice the odd-mode impedance. It is not twice the isolated-line characteristic impedance. For a symmetric coupled pair, the differential impedance can also be written as Zdiff = 2Z0(1 - k).

In contrast to odd-mode transmission, consider the case in which the two adjacent transmission lines carry a common-mode signal, so i1 = i2. Applying the same voltage relations gives:

(13)   V1 = Z0 × (1 + k) × i1

(14)   V2 = Z0 × (1 + k) × i1

This defines the even-mode impedance:

(15)   Zeven = V1 / i1 = Z0 × (1 + k)

The even-mode impedance is the effective characteristic impedance of one line in a coupled pair when both lines carry the same current. The odd-mode impedance is lower than the isolated-line characteristic impedance, while the even-mode impedance is higher. This behavior follows directly from the signs of the coupling terms in the voltage equations. The stronger the coupling, the larger the coupling coefficient k and the greater the separation between odd-mode and even-mode impedance.

These results provide an intuitive understanding of odd-mode, even-mode, and differential impedance. A more complete treatment requires a mathematical derivation based on the distributed parameters of the coupled transmission lines.

 

Coupled-Line Model and Mathematical Derivation

To derive the odd-mode impedance, even-mode impedance, and differential impedance rigorously, ignore the losses on the transmission lines and establish the coupled transmission-line model shown below.

Figure 4 | Model of coupled transmission lines

Figure 4 | Model of coupled transmission lines

In this model, L1 and C1 are the distributed inductance and distributed capacitance of one transmission line when the other transmission line is present. L12 and C12 are the coupling inductance and coupling capacitance between the two transmission lines. L0 and C0 are the distributed inductance and distributed capacitance of a single transmission line when the other line is not present.

The capacitive coupling coefficient is Kc = C12 / C1. The inductive coupling coefficient is Kl = L12 / L1.

For transmission line 1, the transmission-line equations are:

(16)   -dU1/dz = jωL11I1 + jωL12I2

(17)   -dI1/dz = jωC11U1 - jωC12U2

In these equations, L11 = L1 and C11 = C1 + C12.

When an odd-mode signal propagates, U1 = -U2 = Uo and I1 = -I2 = Io. The transmission-line equations become:

(18)   -dUo/dz = jωL11(1 - Kl)Io

(19)   -dIo/dz = jωC11(1 + Kc)Uo

Comparing these equations with the standard telegrapher's equations gives the odd-mode impedance and the odd-mode phase velocity:

(20)   Zodd = √[L11(1 - Kl) / (C11(1 + Kc))]

(21)   vodd = 1 / √[L11C11(1 - Kl)(1 + Kc)]

Similarly, when an even-mode signal propagates, the corresponding results are:

(22)   Zeven = √[L11(1 + Kl) / (C11(1 - Kc))]

(23)   veven = 1 / √[L11C11(1 + Kl)(1 - Kc)]

These equations show how coupling affects both the inductive and capacitive terms. In odd mode, the effective inductance is reduced by the factor (1 - Kl), while the effective capacitance is increased by the factor (1 + Kc). Both changes lower the impedance. In even mode, the effective inductance is increased by (1 + Kl), while the effective capacitance is reduced by (1 - Kc). Both changes raise the impedance. This is the physical reason why odd-mode impedance is lower than the isolated-line impedance and even-mode impedance is higher.

Because the analysis concerns a TEM wave, the even-mode phase velocity veven and the odd-mode phase velocity vodd are equal, and both are equal to the phase velocity of the isolated single line. Setting the two phase-velocity expressions equal gives:

(24)   L11C11(1 - Kl)(1 + Kc) = L11C11(1 + Kl)(1 - Kc)

This equality requires Kl = Kc = K, where K is the coupling coefficient. The propagation product of the isolated line and the coupled line is then related by:

(25)   L0C0 = L11C11(1 - K × K)

According to the characteristics of the magnetic field distribution, when another line is present for coupling and that line is not a magnetic material, the field distribution is not significantly affected. Therefore, the self-inductance of the line in the coupled pair is approximately equal to that of the isolated line:

(26)   L11 ≈ L0

Substituting this relation into equation (25) gives:

(27)   C11 = C0 / (1 - K × K)

Let Z0 = √(L0/C0) be the characteristic impedance of the isolated single line, and let the characteristic impedance of one line in the coupled pair be based on its distributed parameters. Using equations (20), (22), (26), and (27), together with Kl = Kc = K, the following results are obtained:

(28)   Zodd = Z0(1 - K)

(29)   Zeven = Z0(1 + K)

These results are identical to the even-mode and odd-mode impedance expressions obtained from equations (11) and (15). This agreement confirms that the derivation is correct. For a symmetric coupled pair, the differential impedance follows directly as Zdiff = 2Zodd = 2Z0(1 - K).

 

Practical Impedance Control and Reflection

The derivation above is theoretical. In practice, the delay and characteristic impedance of a transmission line are calculated from the cross-sectional geometry of the PCB trace and the dielectric material used. The formulas above are the basis for those calculations. The specific calculation method follows the relevant impedance-control specification.

Because PCB trace manufacturing is constrained by factors such as maximum dielectric thickness and minimum trace width, circuit boards commonly control characteristic impedance within the range of 40 to 75 Ω. The output resistance of a device is generally around ten-plus ohms. Therefore, when series source termination is used, a resistor of about 33 Ω is typically selected to match the trace impedance.

Impedance discontinuity is the root cause of reflection. Reflection produces overshoot and ringing. Overshoot concentrates a large amount of energy, and ringing together with overshoot contains many harmonic components, which have an adverse effect on EMC design. Practical experience shows that reducing overshoot and ringing can effectively reduce conducted and radiated interference. Impedance mismatch caused by layer changes, multiple-load branches, or crossing a split plane also causes signal-quality problems. When these mismatch sources are resolved, most EMC problems are resolved as well. Signal frequency and rise/fall rate are also important factors affecting reflection and EMC. For high-speed signals, impedance should therefore be kept continuous.

Manufacturing Process Impact on Impedance Control

Fabrication process has a strong influence on controlled impedance. In theory, continuously adjusting the dielectric thickness would produce continuously variable impedance. In production, this is difficult for PCB manufacturers to achieve. Many manufacturers in China build boards by lamination, so dielectric thickness is not a continuous variable; it is selected from discrete core and prepreg specifications. Most PCB manufacturers use two dielectric materials: copper-clad core and prepreg. Alternating core and prepreg layers forms the finished board. A typical eight-layer construction is shown below.

Figure 5 | Alternating arrangement of core material and prepreg

Figure 5 | Alternating arrangement of core material and prepreg

The core is a dielectric with copper foil on both sides, essentially a simple double-sided board. Common core thicknesses include 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.2 mm, 1.5 mm, 1.6 mm, 2.0 mm, and 2.4 mm. When performing impedance control, confirm whether the core thickness includes the copper foil thickness. The dielectric value used for impedance calculation must represent the actual dielectric between copper features, not a nominal laminate callout that may include copper.

Prepreg is available in standard styles such as 1080, 2116, and 7628. At least two prepreg sheets should be combined. During lamination, prepreg resin flows, and the dielectric layer becomes thinner than the sum of the individual sheets. Impedance calculations must also account for the signal-layer copper foil embedding into the dielectric during lamination, while plane layers are not affected. The final dielectric thickness after lamination, not the nominal prepreg thickness before lamination, should be used in the impedance model.

Impedance is determined by the self-inductance, self-capacitance, mutual inductance, and mutual capacitance of the PCB trace. These parasitic parameters are closely related to the base material and the manufacturer's processing. Process capability therefore directly affects impedance control accuracy. Theoretically, impedance should be uniform along a single trace. In practice, trace width and dielectric thickness vary with processing, so impedance at different points on the same trace is not identical. Because the stackup uses fixed core and prepreg options, an impedance target must be met by selecting an available combination of dielectric thickness and trace geometry. The same impedance design can therefore yield different results across board houses or across process shifts.

Microstrip lines radiate more readily and are more susceptible to interference than stripline. Critical signals with strong periodicity, such as clocks and low-order address lines, should therefore be routed as stripline, with impedance continuity maintained along the route.

Heavy loading also affects characteristic impedance. In general, excessive capacitive load lowers characteristic impedance and increases trace delay.

Related Reading:

Alex Chen | PCB Design & High-Speed Engineering Specialist Alex Chen | PCB Design & High-Speed Engineering Specialist

Alex Chen is a senior PCB design engineer with extensive experience in high-speed and high-density circuit design. He specializes in signal integrity, impedance control, and multilayer PCB layout optimization. At AIVON, he reviews and refines content related to PCB design principles, EDA tools, and advanced layout techniques. His expertise helps engineers avoid common design pitfalls and improve performance, reliability, and manufacturability in complex PCB projects.

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