Plane splits and slots are common features in PCB stack-ups, yet they are also among the most frequent causes of signal-integrity and EMC problems. A slot may be created deliberately when a power or ground plane is divided into separate nets, or unintentionally when dense via arrays and connector pins leave overlapping isolation rings in a reference plane. This article explains how such slots form, how they affect return-current paths and EMC performance, and what design and process measures can prevent or mitigate the problems. It covers high-speed and low-speed return-current distribution, the role of split grounds, bridging across slots, connector placement, high-density connectors, and quiet-ground partitioning for external I/O.
Highlights:
- Slots arise from power and ground plane splits and from dense via or connector antipads; they interrupt return current and can create crosstalk, common-mode radiation, and impedance discontinuity.
- High-speed return current follows the lowest-impedance path and concentrates beneath the trace; split-plane crossings enlarge the current loop, increase inductance, and degrade signal integrity.
- Use split grounds only for incompatible circuits, never route impedance-controlled high-speed traces across splits, bridge unavoidable crossings, keep external connectors off ground-plane seams, and handle quiet-ground I/O with differential pairs or explicit return paths.
Causes of Slots
Slots are a common structural feature in PCB design. What is usually called a split-plane crossing problem is, in fact, also a slot problem. Slot formation can be grouped into two situations.
Splits in Power and Ground Planes
When a PCB contains multiple power or ground nets, it is generally impractical to assign a complete plane to every power net and every ground net. A common practice is to split one or more planes into separate power or ground regions. The boundaries between different splits on the same plane form slots.
Dense Via Arrays Create Slots
Vias include pads and through holes. When a via passes through a ground or power plane without an electrical connection to that plane, a clearance area, or isolation ring, must be left around the via for electrical isolation. When vias are placed too close together, their isolation rings overlap and form a slot. This is also referred to as the thermal-pad problem. Figure 1 illustrates a slot formed by a dense via array.
Figure 1 | Vias that are too densely packed form a slot.
Figure 1 shows the mechanism clearly. 2mm connectors, or other high-density connectors, are widely used on current boards. When such a connector passes through a power or ground plane, each pin must be isolated from the plane by an isolation ring to achieve effective electrical isolation or safety isolation. When the isolation-ring radius exceeds 1mm, which is half the pin pitch, adjacent rings merge and a slot is formed.
Impact of Slots on EMC Performance
Slots affect the EMC performance of a PCB. The effect may be negative or positive. Therefore, slot placement should be carefully considered during PCB EMC design.
Surface Current Distribution for High-Speed and Low-Speed Signals
At low speed, current flows along the path of least resistance. Figure 2 shows a low-speed current flowing from A to B while its return current returns to the source through the ground plane. In this case, the surface current distribution is broad.
Figure 2 | The return current of a low-speed signal flows along the path of least resistance.
At high speed, the effect of inductance on the return path exceeds that of resistance. The high-speed return current follows the path of lowest impedance. Figure 3 shows a typical high-speed return path.
Figure 3 | The high-speed return signal flows along the path of least impedance. In this case, the surface current distribution is very narrow, and the return signal is concentrated in a bundle beneath the signal line.
In this case, the surface current distribution is narrow, and the return current is bunched in a concentrated band beneath the signal trace.
The Concept of Split Ground
When incompatible circuits coexist on a PCB, ground partitioning is required. Separate grounds are established according to supply voltage, digital and analog signals, high-speed and low-speed signals, and high-current and low-current signals.
The purpose of split ground is easy to understand from the high-speed and low-speed return-current distributions described above. Ground partitioning prevents return currents from incompatible circuits from superimposing and prevents common-ground impedance coupling.
Two Important Points
First, the concept of split ground differs from the problem of a signal crossing a slot in a power or ground plane, which is discussed below. Split ground merely assigns separate ground traces, or planes, to different signal types.
Second, split ground does not completely isolate the various grounds with no electrical connection at all. After partitioning, the grounds are still connected at suitable locations to maintain the electrical continuity of the entire ground layer.
Signal Crossing a Slot in a Power or Ground Plane
Neither high-speed nor low-speed signals should be routed across a split. A split-plane crossing creates several serious problems:
- It increases the current-loop area and the loop inductance, making the output waveform prone to oscillation.
- It increases radiated interference into space and makes the circuit more susceptible to external magnetic fields.
- It increases the possibility of magnetic coupling with other circuits on the board.
- The high-frequency voltage drop across the loop inductance becomes a common-mode radiation source and produces common-mode radiation through attached cables.
For high-speed signal lines that require tight impedance control and are routed according to a stripline model, a slot in the upper plane, the lower plane, or both planes breaks the stripline model. This causes impedance discontinuity and serious signal-integrity problems.
Handling Slots
The following principles should be followed when dealing with slots.
Impedance-Controlled High-Speed Traces Must Not Cross Splits
Routing a high-speed trace across a split causes impedance discontinuity and severe signal-integrity problems. For high-speed lines that require strict impedance control, the trace must never cross a split.
Use Split Grounds for Incompatible Circuits
When incompatible circuits exist on a PCB, ground partitioning should be applied. However, the split ground should not force high-speed signal lines to cross a split, and it should also be arranged, as far as possible, to avoid split crossings by low-speed signal lines.
Bridge When a Crossing Is Unavoidable
When a signal line cannot avoid crossing a slot, effective bridging should be provided. The ground plane should be connected along the direction of the signal path. Figure 4 shows the bridging approach. If a split crossing is unavoidable, it is best to provide a bridge.
External Connectors Must Not Sit on Ground-Plane Seams
Connectors that interface to the outside world should not be placed on a seam in the ground plane. Figure 6(a) shows an incorrect connection, and Figure 5(b) shows the correct connection.
Figure 5(a) | If a large potential difference exists between points A and B on the ground plane in Figure 5(a), common-mode radiation may be generated through an external cable. Therefore, the mounting method in Figure 5(b) should be used i
In Figure 5(a), if a significant potential difference exists between points A and B on the ground plane, common-mode radiation may be produced through an external cable. The connector should therefore be mounted as shown in Figure 5(b), so that no potential difference appears between points A and B.
High-Density Connectors
When a high-density connector, such as the widely used 2mm connector, passes through power and ground planes, an excessively large isolation-ring radius can form a slot, as shown in Figure 1. During PCB design, unless there is a special requirement, such as a strict safety distance for an individual signal, the ground net should generally surround every pin. Alternatively, ground pins can be distributed evenly during pin assignment to preserve ground-plane continuity and prevent slot formation.
Crossing a Quiet-Ground Split
For I/O signals that leave a subrack or cabinet through cables, shielding and filtering require a clean ground that is not polluted by internal noise. Without this quiet ground, filtering of high-frequency signals is almost ineffective. The quiet ground can be a metal frame or protective ground. It is not connected to the board's internal logic ground.
Once a quiet ground is established on the PCB, I/O signal lines inevitably have to cross the quiet-ground split, and some treatment is required.
For differential signal pairs, routing across the quiet-ground split can effectively suppress common-mode noise, and no special treatment is needed.
For ordinary signal lines, a return path must be provided. During PCB routing, the GND net brought out from the interface device should be treated as an ordinary signal line. Figure 9 shows a simple routing example for an RS-232 serial port.
Case Study: ESD Reset Caused by a Split-Plane Crossing
A test on a PON product illustrates the problem. The investigation sought to determine why a tributary board with GND connected to earth reset easily. The DMU had both PGND and GND, and the two grounds were not connected on the board. The hard-reset input lead of the ADM706 crossed the two grounds. The lead was routed on layer 1 of the PCB, while the two grounds were on layer 2. Under external interference, a potential difference could easily develop between the two grounds. The lead was cut and reconnected with a flying wire. With GND connected to earth, the ESD test was repeated using contact discharge on the rear panel of the enclosure. The tributary board did not reset at ±6000V.
In the initial DMU design, the reset signal crossed the split between PGND and GND. During ESD testing, discharge to the chassis, including the handle bar, caused repeated resets. During the board revision, the ground split was corrected to eliminate the reset-signal split crossing. The next ESD test passed, and at 6000V the reset circuit continued to operate normally.
Related Reading:
- Capacitor Selection and Placement for PCB EMC Design
- Surface Microstrip vs. Inner-Layer Stripline Routing
- Impedance Control Basics: Characteristic Impedance Explained
- Special Signal Handling and Via Effects in PCB Design
- Backplane Slot Layout and Board Position Structure for EMC Design
- Backplane Connector, Impedance, and Power/Ground Design for EMC
- PCB EMC Design: Module Partitioning and Special Component Layout
