Special Signal Handling and Via Effects in PCB Design

In PCB electromagnetic compatibility (EMC) design, not every net receives the same level of attention. Most of the engineering effort is directed at a limited set of special signals, and the way those signals are routed, referenced, and returned determines much of the board's EMC behavior. Vias are one of the most common features that disturb this behavior. This article explains how special signals are classified, how a via can be represented as a parasitic model, how via impedance discontinuity affects signal integrity and radiation, and which layout measures are used to control the effect.

Highlights:

A via is a vertical interconnect with parasitic capacitance and inductance; small vias have lower parasitic capacitance, but every via still creates a local impedance discontinuity.
TDR measurements show a 6 to 7 Ω transient impedance drop at a via, giving a negative reflection coefficient of about 0.055 on a 50 Ω trace, approximately 5%.
Sensitive nets should change layers only when necessary; nearby ground vias or ground guarding reduce return-path discontinuity, and for signals below 1 GHz inner-layer routing is preferred to limit radiation.

Special Signal Handling

In PCB EMC design, the main work is concentrated on handling a small number of special signals. From the relationship between the signal and the external environment, signals can be divided into strong signals and small, weak signals. From the signal type, the nets that require attention include clocks, buses, I/O, resets, interfaces, power, and ground.

Vias

A via is a vertical connection between PCB layers. At low frequencies it behaves almost as an ideal connection, but at high frequencies its geometry introduces parasitic elements that affect the transmission line.

Via Model

Past PCB designs show that vias have little effect on low-frequency, low-speed signals. More recently, as clock speeds have increased, device rise time and timing have become key PCB design issues. The effect of vias in PCB transmission lines has therefore become a widely discussed topic. The figure below shows a via model for a PCB.

Mathematical Model of a Via

Like a conventional transmission line, a via can be represented by a parameter model composed of capacitance, inductance, and resistance. The via model can be extracted with a field extraction tool such as ANSOFT, or measured with time-domain reflectometry (TDR). The calculation formulas are:

C = 1.41 ε_r T D₁ / (D₂ ? D₁)

D₂: diameter of the via region, in inches; D₁: via pad diameter, in inches; T: PCB thickness, in inches; ε_r: dielectric constant; C: via parasitic capacitance, in pF.

It follows that a small via has a smaller parasitic capacitance.

L = 5.08h [ln(4h/d) + 1]

h: via length, in inches; d: via diameter, in inches; L: via parasitic inductance, in nH.

In simulation analysis, the via model is often approximated by a 1 pF capacitor. TDR measurement shows a transient impedance drop of 6 to 7 Ω.

Factors Affecting the Via Model

The formulas show that the main factors affecting via parameters are via diameter, board thickness, and via pad size. Other factors include different layer settings, the layer at which the via changes layers, and the influence of plane layers.

Via Effects on Signal Conduction and Radiated Emission

A via carries the signal from one layer to another, but it also interrupts the reference plane and changes the return-current path. The following discussion focuses on impedance control and on layout measures that reduce the discontinuity.

Via Effects on Impedance Control

Devices that require drilled holes in the PCB, and vias drilled in the PCB, both cause discontinuity of the reference (image) plane and destroy the optimum return path for the signal. A detailed example is shown below:

For microstrip or stripline that must be routed through vias between different layers, fixed RF return paths exist around the traces, and these paths are easily disturbed. The easiest way to improve immunity is not to route through vias between layers; routing on the same layer is best. Ensure that no impedance discontinuity is caused at any point between the microstrip and the ground plane. If a sensitive signal line must use a via, place a ground via near the signal via to reduce the discontinuity. Consider a board with four or more layers: one complete ground layer, one complete power layer, and other routing layers. To ensure good signal return during routing, the ground layer should serve as the main return path. If a sensitive signal must pass through a via to an adjacent layer other than the ground layer, apply ground guarding to that signal line. The guard ground trace should be parallel to the signal line and as close as possible.

The known negative effects of vias can be grouped into the following categories:

A via is an inherent capacitance and therefore changes the characteristic impedance of the PCB trace.
A via causes a jump in the characteristic impedance of the trace and therefore causes reflection. The via produces a 6 to 7 Ω transient impedance discontinuity on the trace, which results in a negative reflection coefficient of about 0.055 (for a trace characteristic impedance of about 50 Ω), approximately 5%.
When a trace changes from one layer to another, the reference plane changes and the return path of the trace also changes. The characteristic impedance of the trace may change substantially.
If a trace on one layer goes to another layer with the same reference plane, the via effect is smaller; otherwise, when the reference plane changes after the layer change, the characteristic impedance of the transmission line may change substantially.

Unfortunately, few dedicated studies have examined the effect of vias in PCB routing while keeping other parameters unchanged. This is caused, at least in part, by the following resource limitations:

A test PCB must be designed.
The board must be fabricated.
A good test instrument is required, and the researcher must be able to use it skillfully.

Impact of Via Count on Signal Quality

The effect of via count on signals still requires verification. In practice, every via, and even the trace itself, contributes some high-frequency loss. TDR results show that a via does have a capacitive effect, causing attenuation of higher harmonics and a slower signal rise time. For a single via, however, the attenuation it causes is negligible compared with the attenuation of the entire trace. For designers using components with rise times in the range of 0.5 ns to 1.0 ns (500 ps to 1000 ps), or faster, the edge slowing of a few tens of picoseconds caused by one via has relatively little effect. For very high-speed designs, the effect of multiple vias should be considered, and the number of vias should be minimized.

Vias also increase signal transmission time. In general, one via contributes about a few hundred picoseconds of trace delay. For long traces on a backplane, the effect of one via is also negligible.

Recommendations for vias in PCB design:

Minimize the number of vias.
When changing routing layers, give preference to planes that provide continuous impedance.
For signals below 1 GHz, give priority to inner-layer routing to reduce radiation effects rather than avoiding vias.

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