Once the overall hardware architecture of a system is fixed, the number and types of line cards are fixed as well, and every signal that must reach the backplane is already determined. From that point on, the PCB designer has to work with two coupled decisions: where each card sits in the backplane, and how each signal leaves its card and travels across the backplane. Together these decisions determine whether the mother board meets its performance targets and whether it satisfies EMC requirements at the same time.
Signal velocity dictates much of that reasoning. High-speed traffic is normally demultiplexed into slower traffic at the card boundary, so the backplane carries a mixture of fast and slow nets that must not be allowed to corrupt one another. Slot assignment therefore has to account for the influence of the high-speed portion on the low-speed portion, and the routing topology has to be chosen so that reflections stay under control. This section covers how slot placement, board position structure, topology selection, termination strategy, and driver technology interact on a real backplane.
Highlights:
- High-speed card positions and low-speed card positions should be physically separated on the backplane, with short high-speed routing and shielding applied to the high-speed boards where appropriate.
- Every impedance discontinuity (right-angle bends, vias, connectors, IC packages) produces reflections whose impact scales with system speed; topology and termination are the primary tools for keeping that impact small.
- Backplane signal levels and driver devices must be selected at the architecture stage, matched to the required data rate and to the number of loads the backplane has to drive.
EMC Design of the Backplane
Arranging Backplane Slots
Interconnection Requirements Between Cards
When the overall hardware scheme is settled, the types and quantities of line cards are known and all signals routed onto the backplane are defined. In the PCB design phase, the designer must consider both the position of each card slot and the way signals leave each card, so that the mother board achieves its performance specification while still meeting EMC requirements.
Signals differ in rate: high-speed traffic is demultiplexed into low-speed traffic, and the board-position assignment on the backplane has to take the influence of the high-speed portion on the low-speed portion into account. From an EMC design standpoint, the high-speed portion couples into the low-speed portion by conduction or by radiation, and in the worst case the design simply cannot function. High-speed image (return) currents must be prevented from flowing into low-speed circuit areas, and critical traces, especially high-frequency and high-speed lines, high-current lines, and strong-signal lines, must be kept as short as possible.
The consequence for slot layout is straightforward: high-speed slots and low-speed slots should be separated, high-speed routing should be short, and high-speed cards may be shielded where the interference risk justifies it.
A typical product illustrates the principle. The system is divided into high-speed transceiver cards, a management and processing unit card, a cross-connect card, a clock card, a main control card, and tributary cards. Collectively these implement multiplexing and demultiplexing, frame scrambling and descrambling, overhead processing, clock selection, and cross-connection. According to the interconnection requirements between the cards, the high-speed portion and the low-speed tributary processing portion are split into an upper half and a lower half. The high-speed transceiver cards are placed at the edge slots of the high-speed section, which reduces the interference that high-speed transceiver signals inject into the interior of the system, and the high-speed portion of those transceiver cards is additionally shielded.
Board Position Structure
How Board Position Structure Affects Signal Quality
When a pulse is launched from a source, the amplitude along the line is set by the voltage divider formed between the source's internal resistance and the impedance of the transmission line.
When the incident wave arrives at the load, part of the energy is reflected back toward the source. The reflected energy is governed by the reflection coefficient, and the reflection coefficient is governed by the impedance of the transmission line and the impedance of the load.
The reflection coefficient lies between -1 and +1. An open circuit has a reflection coefficient of +1: the incident wave reaching an open load is reflected back to the source with the same phase, and the voltage amplitude at the load becomes twice the incident amplitude. A short circuit has a reflection coefficient of -1: the incident wave reaching a shorted load is inverted and returned to the source in the opposite phase, and the voltages superimpose to zero volts at the receiving end. A termination that keeps the line impedance continuous is called a match; the reflection coefficient is then zero, no reflection occurs, and the signal amplitude at the load equals the amplitude of the incident signal.
A signal also encounters other discontinuity points along its path. Right-angle corners, vias, connectors, and IC packages can all disturb the waveform that would otherwise be clean. The severity of these impedance discontinuities is set by the speed of the system. At low speed their contribution may be negligible; at high speed the result can become very pronounced.
In most cases the driver is the dominant noise source, and that noise can be handled through an appropriate topology combined with proper termination. The available topologies are point-to-point, tree, T, star, and daisy chain.
- Tree structure: long branches are prone to overload and ringing.
- Daisy chain: well suited to bus driving with parallel termination at the end of the line; T-shaped branches should be avoided wherever possible.
- Star: requires a buffer with high drive capability (low output impedance) and uses series matching.
Adopting a suitable topology reduces reflection, improves signal quality, and lowers EMI. On a backplane this is harder than on a point-to-point link, because the presence of working and protection cards means multiple loads are unavoidable. Arranging slots so that the resulting routing topology is reasonable and reflections stay small is therefore a central concern of backplane design. Clock lines in particular should be driven point-to-point wherever possible, avoiding a bus arrangement entirely. Point-to-multipoint driving calls for termination. For reasons of manufacturability and maintenance, impedance matching should in principle be handled on the line card itself, and implemented on the backplane only when there is no alternative, with as few components as possible placed on the backplane.
A service interface protection subsystem shows how topology revision changes the outcome. The original design used a 1:8 transmit and 8:1 receive arrangement. Simulation showed that, given the board position structure on the backplane, the topology would be unbalanced and the signal quality at the near-end load could not be guaranteed. After discussion with the hardware developers, the clock was changed to a 1:4 transmit and 4:1 receive configuration with a revised topology, which produced four reasonably balanced loads; in addition, the trace length from the load-side connector to the interface device had to be strictly controlled to within 2000mil. The matching scheme was then confirmed through extensive simulation and comparison. On the transmit side, resistor-capacitor filter matching is applied at the driver and a series resistor at the end suppresses ringing: the waveform edges become slightly gentler, but the rise and fall distortion is eliminated. On the receive side, series matching is used at the driver and a large series resistor is placed at the end, with the value taken as the characteristic impedance of the trace multiplied by the number of branches. The resulting waveform is good, with only a fairly large undershoot, which can be controlled by adjusting the value of the matching resistor.
Inter-board Interconnect Levels and Driver Selection
Backplane signal levels and driver devices should be decided while the overall scheme is still being defined. The chosen level must satisfy the transmission rate required on the backplane. For transmission rates below 100 Mb/s with multiple load structures, GTL+ is a practical choice; among devices that meet the requirement, those with lower drive current should be preferred, since they make EMI easier to control. For example, the drive current of TI's GTL1655 and GTL16923 differs by nearly a factor of two. For signal rates of a few hundred Mb/s, LVDS is a strong option: its common-mode interference rejection and matching method are easy to satisfy, its current-mode operation gives good noise immunity, and the small differential swing greatly reduces both power consumption and EMI. Above 1 GHz, ECL or CML levels are normally used, and these can carry signal rates beyond 2.5 Gb/s across a backplane built from ordinary board material.
Naturally, high-speed backplane design places stricter demands on impedance control, routing constraints, and EMC control. Differential signal pairs must be routed on the same layer, run closely coupled and parallel, and follow the 3W rule and strict length-matching principles with respect to other traces. Adjacent high-speed differential pairs should be separated by ground.
- Transmission Line Models: Microstrip, Stripline, and Reflections
- Surface Microstrip vs. Inner-Layer Stripline Routing
- Special Signal Handling and Via Effects in PCB Design
- Backplane Slot Layout and Board Position Structure for EMC Design
- PCB EMC Design: Module Partitioning and Special Component Layout
- Filter Components and Filter Circuit Design in PCB EMC Engineering
- Handling Split-Plane Crossings and Slots in PCB Design
- Grounding Concepts and Methods for PCB and Backplane Design
