Transmission Line Models: Microstrip, Stripline, and Reflections

In high-speed digital PCB design, a copper trace stops behaving as a simple electrical connection once the signals it carries change fast enough or travel far enough. At that point the trace must be treated as a transmission line, because the voltage and current along it are no longer uniform and its routing geometry begins to dominate signal quality. Two transmission line types appear on essentially every high-speed board: the microstrip, routed on an outer layer beside a reference plane, and the stripline, buried between two reference planes. The characteristics that matter most for EMC-aware design are characteristic impedance, propagation delay, intrinsic capacitance, and intrinsic inductance. Reflections and crosstalk degrade signal quality, and from an EMC standpoint they are also a primary source of EMI. This article explains when a trace becomes a transmission line, how the two fundamental line types are modeled, and how the design equations for impedance, delay, capacitance, and inductance differ between microstrip, stripline, and embedded microstrip geometries.

Highlights:

• A PCB trace behaves as a transmission line when its routing length exceeds one-twentieth of the signal wavelength or its propagation delay exceeds one-sixth of the signal rise time.
• Microstrip lines (outer layers) and stripline lines (inner layers between two planes) are the two fundamental transmission line types, and each has its own set of equations for characteristic impedance, propagation delay, intrinsic capacitance, and intrinsic inductance.
• Reflections and crosstalk distort signal quality and are a main source of EMI, so controlled impedance and delay analysis sit at the center of EMC-conscious routing.

When a PCB Trace Becomes a Transmission Line

The decision to model a trace as a transmission line depends on the relationship between the physical length of the route and the electrical behavior of the signal. In high-speed digital PCB design, a trace is treated as a transmission line when its routed length is longer than one-twentieth of the signal wavelength, or when the signal delay through the trace exceeds one-sixth of the signal rise time. Both criteria express the same underlying idea: once the round-trip delay along the trace is no longer small compared with the edge transition, the instantaneous voltage along the line is no longer the same at every point, and the distributed nature of the trace cannot be ignored.

Under these conditions the trace is no longer described by a single lumped impedance. Instead it is described by its distributed parameters, and it can carry reflections and coupling that alter the waveform reaching the receiver. The line types themselves fall into two broad categories: microstrip and stripline. Each category is characterized by a defined set of properties that relate geometry and dielectric material to the electrical performance of the trace. The properties most relevant to EMC design are characteristic impedance, propagation delay, intrinsic capacitance, and intrinsic inductance. These four quantities are not independent; they are linked through the geometry of the trace and the dielectric constant of the material surrounding it, which is why changing one dimension inevitably shifts the others.

Reflections and crosstalk are the two dominant signal integrity effects that emerge once a trace is treated as a transmission line. Reflections arise from impedance discontinuities along the path, and crosstalk arises from the electromagnetic coupling between adjacent traces. Both distort the signal that arrives at the receiver, and both radiate. From the EMC perspective, these two effects are among the primary sources of EMI on a high-speed board, which is why they are analyzed together with the transmission line model rather than as separate topics.

Transmission Line Model

A full derivation of the distributed-parameter transmission line model is outside the scope of this discussion, and the model itself is a standard subject in signal quality control procedures. For practical routing work, the model is used in its working form: each line type is represented by closed-form equations that relate the trace geometry and the dielectric constant to characteristic impedance, propagation delay, and the per-unit-length parasitic elements. The following sections apply this working model to each line type so that the designer can compare geometries directly.

Types of Transmission Lines

Microstrip Line

A microstrip line is defined as a surface-layer trace adjacent to a reference plane. Because one side of the trace faces the air and the other side faces the dielectric, the electromagnetic field is split between two media. This asymmetry distinguishes the microstrip from the stripline and affects every value derived from the geometry.

Characteristic impedance:

Z0 = (87 / √(εr + 1.41)) · ln(5.98h / (0.8w + t)) Ω

Propagation delay:

tPD = 85 · √(0.475εr + 0.67) ps/inch

Intrinsic capacitance:

C0 = 1000 · tPD / Z0 pF/ft

Intrinsic inductance:

L0 = Z02 · C0 pH/ft

For the FR-4 dielectric material commonly used in practice, the propagation delay simplifies to TPD = 142.2 ps/inch. These equations show how the impedance is set by the dielectric constant and by the ratio of the trace height above the plane to the trace width, while the delay is driven mainly by the dielectric constant. The capacitance and inductance follow from the impedance and the delay, so a change in geometry that shifts the impedance also shifts both distributed parasitic elements.

Stripline

A stripline is defined as a PCB trace routed between two reference planes. Because the trace is surrounded by dielectric on both sides, its field distribution differs from that of a microstrip, and the impedance and delay equations reflect this geometry.

Characteristic impedance:

Z0 = (60 / √εr) · ln(4h / (0.67πw(0.8 + t/w))) Ω

Propagation delay:

tPD = 1.017 · √εr ns/ft, or equivalently 85 · √εr ps/inch

Intrinsic capacitance:

C0 = 1000 · tPD / Z0 pF/ft

Intrinsic inductance:

L0 = Z02 · C0 pH/ft

For the commonly used FR-4 dielectric material, the propagation delay equation simplifies to TPD = 180.3 ps/inch. Comparing this with the microstrip result shows that, for the same dielectric material, the fully embedded stripline produces a longer delay per unit length. The designer therefore gains shielding and a more controlled field distribution at the cost of a slower signal, which is a trade-off that must be weighed when selecting layer assignments for high-speed nets.

Embedded Microstrip Line

An embedded microstrip is a surface-layer trace that is covered by a dielectric layer rather than exposed to air. This covering changes the field distribution and introduces an additional geometric parameter, so the characteristic impedance is calculated as follows:

Z0 = (K / √(0.805εr + 2)) · ln(5.98h / (0.8w + 1)) Ω

where 60 ≤ K ≤ 65.

The coefficient K depends on the embedding thickness. It decreases as the embedding thickness increases: below 15mil, K = 65, and at 20mil, K = 60. This means that the impedance of an embedded microstrip is not fixed by the trace width and dielectric constant alone; the thickness of the covering layer must also be known before the impedance can be calculated.

Alternatively, the characteristic impedance can be computed using the following form:

Z0 = (87 / √(εr' + 1.41)) · ln(5.98h / (0.8w + t))

with an effective dielectric constant given by:

εr' = εr [1 - e^(-1.55B / b)]

In this alternative formulation, the covering layer is accounted for through the effective dielectric constant rather than through a separate coefficient. Both approaches describe the same physical situation: the presence of dielectric above the trace pulls more of the field into the material and therefore changes the impedance and the delay compared with an exposed microstrip.

The propagation delay of the embedded microstrip is approximated by:

Tpd ≈ 0.0339 · √(0.475εr + 0.67) ns/cm

Taken together, these three line types cover the geometries a high-speed designer meets most often. The microstrip and the embedded microstrip share the surface-layer arrangement but differ in whether the trace is exposed to air or covered by dielectric, while the stripline places the trace between two planes and gives the most uniform field distribution of the three. In every case, the characteristic impedance, propagation delay, intrinsic capacitance, and intrinsic inductance are tied to the same underlying geometry and material properties, so the equations should be used together rather than in isolation. Understanding these relationships is the first step toward controlling reflections and crosstalk, and toward routing that keeps EMI within acceptable limits.

Transmission Line Reflection and Crosstalk in High-Speed PCB Design

Reflection on Transmission Lines

A trace behaves as a transmission line only for as long as it remains electrically uniform. Any non-uniformity along the propagation path, whether it comes from a change in impedance or from a geometric detail such as a right-angle corner, causes part of the travelling energy to be reflected back toward the source instead of being delivered to the load. The reflected wave does not simply disappear at the driver; depending on the impedance it meets there, part of it is reflected again and travels back toward the receiver. The result depends on the nature of the signal.

For an analog signal, that is, a sine wave, the incident and reflected waves interfere and form a standing wave along the trace, with fixed positions of maximum and minimum amplitude. For a digital signal, which is built from a wide spectrum of frequency components, the same interference appears in the time domain as ringing and overshoot on the rising edge and on the falling edge. The waveform no longer settles immediately at its final level; it oscillates around it before converging.

The consequences go beyond a slightly degraded eye diagram. Overshoot produces strong electromagnetic interference, and at the same time it stresses the protection diodes at the input of the downstream circuit. Each excursion beyond the supply rail forward-biases the clamping diode; repeated overstress degrades the diode, and in the worst case the device fails altogether. A reflected waveform that looks acceptable on a bench scope can therefore still be a long-term reliability problem for the receiving device.

The waveform below illustrates how the reflection shows up on the edges of a digital pulse:

When Overshoot Requires Corrective Action

As a general engineering rule, once the overshoot exceeds 0.7V, measures should be taken. The threshold is not arbitrary: an excursion of that magnitude is large enough to be a meaningful EMI contributor and to bring an input protection diode close to conduction on every edge. In the circuit shown below, the source impedance and the load impedance are what cause the signal to reflect back and forth between the two ends of the interconnect.

The driver presents a source resistance, the receiver presents a load resistance, and neither of them necessarily equals the characteristic impedance of the trace connecting them. When either end is mismatched, the wave arriving at that end is partially reflected. The mismatch at one end therefore does not stay local to that end, it sets up a round trip whose energy is only gradually dissipated by the resistive losses of the line and the driver.

Reflection Coefficient at the Source and at the Load

The behaviour at each termination is quantified by a reflection coefficient, defined as the ratio of the reflected voltage to the incident voltage at that point. For the source end and the load end respectively:

ρ_S = (R_S - Z₀) / (R_S + Z₀)

ρ_L = (R_L - Z₀) / (R_L + Z₀)

Here R_S is the source impedance, R_L is the load impedance, and Z₀ is the characteristic impedance of the trace. The structure of the expression tells the whole story. When the termination resistance equals Z₀, the numerator becomes zero and the coefficient vanishes, so no energy is returned from that end and the line is matched. When the load is much larger than Z₀, the coefficient approaches +1 and the reflected wave returns with the same polarity as the incident wave; when the load is much smaller than Z₀, the coefficient approaches -1 and the reflected wave returns inverted. The objective of any termination strategy is therefore straightforward: bring the resistance seen at the end of the line as close to Z₀ as possible so that the numerator of the coefficient is driven toward zero.

Matched and Unmatched Circuits Compared

The difference between a terminated and an unterminated interconnect is easiest to appreciate by comparing measured or simulated waveforms side by side. The figures below present that comparison: the same signal path evaluated with and without a matching circuit at the receiving end.

In the unmatched case the edge is followed by a staircase of successive reflections, and the amplitude can rise well above the nominal logic level before the waveform decays to its final value. In the matched case the same edge arrives with the overshoot largely suppressed and the settling behaviour clean. The comparison makes the engineering trade-off visible: the matching network adds components and consumes DC power or board area, and in exchange it removes the overshoot, the undershoot, and the ringing that would otherwise be present on both edges.

Reflection therefore produces overshoot, undershoot, and ringing on the rising edge and on the falling edge of the signal. These excursions are not merely a signal integrity issue, although they certainly are that. They are also a principal source of EMI radiation: the same edge currents that create the visible ringing on the waveform drive the trace as an unintentional antenna. Suppressing the reflection addresses the signal quality problem and the emission problem at the same time, which is why termination is treated as a first-order design decision rather than an optional refinement.

Crosstalk Between Adjacent PCB Traces

Consider the circuit shown below, in which two adjacent PCB traces run in parallel. Between them there is a parasitic capacitance, C_SV. A high-frequency signal on one trace couples through that capacitance into the other, so that when a pulse travels along the first trace, a disturbance appears on the second trace at the positions corresponding to the rising and falling edges of that pulse. This is crosstalk between PCB traces.

Crosstalk degrades signal quality on the victim line, and its effect is not limited to a single edge: the coupled pulses appear wherever the aggressor transitions, so a data stream produces a continuous train of coupled disturbances. More importantly, those crosstalk pulses are also a major source of EMI emission. The coupling path that carries energy from one trace to its neighbour also carries energy off the board. The figure below shows the geometry used to describe and predict trace-to-trace crosstalk for EMI purposes.

That geometry defines the parameters that control how much energy is coupled. It is a field problem rather than a circuit problem, which is why the list of influencing factors mixes electrical, material, and layout quantities.

Factors That Determine Crosstalk Amplitude

The parameters that influence crosstalk between transmission lines are:

• The coupling length L, meaning the distance over which the two traces run in parallel.
• The input and output impedances at the source end and at the load end.
• The dielectric constant of the board material.
• The width W of the transmission line.
• The thickness T of the conductor.
• The height H between the trace and the reference plane.

The same set of factors can be viewed from the other direction, in terms of the parasitic elements they produce: the distributed capacitance C_SV, the parasitic capacitance C_ti, and the coupling inductance L. The geometric view is convenient during layout because width, spacing, and height are the numbers a designer actually controls; the parasitic view is convenient during analysis because those capacitances and inductances are what the field solver reports and what the coupling equations consume.

The two views are linked. The height H above the reference plane sets how tightly the field of each trace is confined, and therefore how much of it is available to reach the neighbouring trace. The width W and thickness T set the cross-section of the conductor that carries the current and therefore its characteristic impedance. The spacing between traces, together with W and H, sets the mutual capacitance. The dielectric constant of the laminate scales the capacitances for a given geometry. Finally, the coupling length L determines how much of the coupled energy accumulates: the effect is cumulative along the parallel run, which is why long parallel runs at small spacing are the classic crosstalk risk in a dense layout.

Tabulated Crosstalk Values for a 100 Ω Victim Line

The table below lists crosstalk values under different conditions, for a victim line impedance of approximately 100 Ω. The columns are organized by the geometry ratio W/h, that is, the ratio of trace width to height above the reference plane. The sub-columns within each group give the spacing ratio W/S. The first column lists the frequency of interest, and the rightmost column gives the rise time of the culprit pulse that corresponds to that frequency.

Three trends are visible in the numbers. Moving down the table, from low frequency toward high frequency, the values become progressively less negative, meaning that crosstalk grows as the edge gets faster. Moving across the table from left to right, that is, from a wide trace with a low height ratio to a narrow trace with a high height ratio, the values also become less negative: a trace that sits far above its reference plane, or that has no reference plane beneath it at all, couples far more strongly than a trace that is tightly coupled to a nearby plane. Moving across the sub-columns within a single geometry, from W/S = 0.1 to W/S = 3, the values again become less negative, which is simply the statement that bringing traces closer together increases crosstalk. The count of least-negative entries sits in the bottom right group, where narrow traces with no close ground return are placed close together at gigahertz frequencies.

The two entries in the column headers deserve attention because they explain the mechanism behind the geometry dependence. For W/h = 5, the coupling capacitance Cvg is 2 pF/cm and the characteristic impedance is 34 Ω; for W/h = 0.3 or for a trace with no ground return underneath, Cvg drops below 0.1 pF/cm while the impedance rises above 120 Ω. This is the practical reason why controlled-impedance design and crosstalk control are the same discussion: a geometry that produces a low impedance by sitting close to a plane also confines the field, keeps the mutual capacitance small, and suppresses coupling.

Reading the Table: Notes and Scaling Rules

The table is generated under a specific set of assumptions, and the notes below define how it should be applied and how it may be scaled to other conditions:

• Epoxy glass is assumed as the dielectric, with a dielectric constant of 4.
• Crosstalk is expressed as 20 log (V_victim / V_culprit) per centimetre of parallel run. For other lengths, add 20 log of the length ratio relative to the reference length.
• For a victim impedance other than 100 Ω, within the range from 10 Ω to 300 Ω, add 20 log (Z_victim / 100).
• Clamp the result to 0 dB, because crosstalk cannot be positive.
• An example of some typical values: W = 20 mils (0.5 mm) and S = 30 mils (0.75 mm). For a single-layer board, h = 30 to 40 mils (0.7 to 1 mm). For a multilayer board, h = 5 mils (0.12 mm).

The scaling rule for impedance is worth reading carefully. A lower-impedance victim receives a negative correction, which reduces the predicted coupling, while a higher-impedance victim receives a positive correction. The clamp at 0 dB is the physical ceiling: coupling cannot exceed the amplitude of the culprit signal itself, so no combination of corrections is allowed to produce a positive decibel figure, and any calculation that does so has been pushed beyond the validity of the model.

The typical values in the final note show how the ratios play out in a real stack-up. With W = 20 mils and S = 30 mils, the spacing ratio W/S is approximately 0.67, which falls between the 0.3 and 1 columns and therefore requires interpolation. On a single-layer board with h between 30 and 40 mils, W/h falls between about 0.67 and 0.5, placing the design in the right-hand, weakly referenced columns; on a multilayer board with h = 5 mils, W/h reaches about 4, placing the same trace width in the left-hand, tightly coupled columns. The same trace width, in other words, moves across the entire table simply by changing the stack-up. That is the quantitative expression of the design rule that high-speed traces need a close reference plane: it is not a matter of convention but a shift of several tens of decibels in the predicted coupling.

Related Reading:

• Surface Microstrip vs. Inner-Layer Stripline Routing
• Impedance Control Basics: Characteristic Impedance Explained
• Special Signal Handling and Via Effects in PCB Design
• Backplane Slot Layout and Board Position Structure for EMC Design
• Backplane Connector, Impedance, and Power/Ground Design for EMC
• PCB EMC Design: Module Partitioning and Special Component Layout
• Filter Components and Filter Circuit Design in PCB EMC Engineering
• Grounding Concepts and Methods for PCB and Backplane Design