Capacitor Selection and Placement for PCB EMC Design

Capacitors are the most widely used components in PCB EMC design. They provide decoupling, bypass, and bulk energy storage, but their parasitic equivalent series inductance (ESL) and equivalent series resistance (ESR) make their actual frequency response far from ideal. A capacitor that looks like a simple low-pass filter on a schematic can behave as a bandpass element around its self-resonant point, and parallel combinations can create anti-resonance peaks that raise impedance over a wide frequency band. This article examines the functions of filter capacitors, the self-resonance and anti-resonance problems that limit their effectiveness, the influence of ESR and ESL, practical capacitor selection, and design recommendations for decoupling, bypass, and bulk capacitors.

Highlights:

Capacitors are the most widely used EMC components on PCBs, but their parasitic ESL and ESR turn simple filtering into a resonance-management problem.
Parallel capacitors can create anti-resonance peaks that increase impedance over a broad band; ESR, ESL, package, and layout determine the peak height and location.
Decoupling, bypass, and bulk capacitors serve different functions and require different selection and placement rules.

Filter Capacitor Types

In PCB EMC design, capacitors are classified by function into three categories:

Decoupling: Decoupling breaks the coupling between ports of a system or circuit to ensure normal operation.
Bypass: A bypass capacitor provides a low-impedance path to ground at the point where transient energy is generated. It is one of the necessary conditions for good decoupling.
Bulk: A bulk capacitor ensures that the voltage does not drop when the load changes quickly to its heaviest condition.

Capacitor Self-Resonance

The capacitors used for filtering are not ideal capacitors. In a system, a real capacitor behaves as a series combination of capacitance, inductance, and resistance, as shown in Figure 3-9.

Figure 3-9 | Schematic diagram of equivalent circuits for ideal and practical capacitors

When a multi-layer capacitor is mounted on a PCB, it introduces nearly 5nH of parasitic inductance, plus about 30mΩ of lead resistance. Its frequency characteristic then follows the curve shown in Figure 3-10. The filter capacitor is no longer an ideal low-pass filter. Its actual insertion loss characteristic behaves as a bandpass filter centered on the self-resonant point.

Figure 3-10 | Actual amplitude-frequency characteristic of a single capacitor

When two capacitors are connected in parallel, the presence of ESL and ESR creates an anti-resonance problem. Figure 3-11 shows the equivalent schematic of parallel capacitors, and Figure 3-12 shows their real magnitude-frequency characteristic.

Figure 3-11 | Equivalent schematic diagram of capacitors in parallel

Figure 3-12 | True amplitude-frequency characteristic of capacitors in parallel

Figure 3-12 shows that over a broad band from nearly 15MHz to 175MHz, the impedance of the parallel capacitors is larger than that of a single large capacitor. Because the two capacitors produce resonance, an impedance peak appears at 150MHz. In that frequency range, only a small portion of the energy generated by other parts of the system can be bypassed to the ground plane.

ESR Effects on Parallel Capacitor Frequency Response

The impedance peak shown in Figure 3-12 is inversely proportional to the ESR of the capacitor. As board design and device performance improve, the impedance peak of parallel capacitors will increase as ESR decreases. The shape and position of the parallel resonance peak depend on PCB design and capacitor selection.

Several principles should be understood:

As ESR decreases, the impedance at the resonance point decreases, but the impedance at the anti-resonance point increases.
When n identical capacitors are connected in parallel, the minimum impedance may be less than ESR/n.
When multiple capacitors are connected in parallel, the impedance does not necessarily occur at the capacitor resonance point.
For a given number of capacitors, a better choice is to spread the capacitance values evenly over a wide range with moderate ESR for each value. A poorer choice is to use only a few capacitance values and make their ESR very small.

ESL Effects on Parallel Capacitor Frequency Response

Capacitor package and structure change ESL. Table 3-1 lists the ESL of several typical capacitor packages.

Type of Capacitor	Residual Inductance (ESL)
Leaded disc ceramic capacitor (0.01 μF)	3.0 nH
Leaded disc ceramic capacitor (0.1 μF)	2.6 nH
Leaded monolithic ceramic capacitor (0.01 μF)	1.6 nH
Leaded monolithic ceramic capacitor (0.1 μF)	1.9 nH
Chip monolithic ceramic capacitor (0.01 μF, Size: 2.0 x 1.25 x 0.6 mm)	0.7 nH
Chip monolithic ceramic capacitor (0.1 μF, Size: 2.0 x 1.25 x 0.85 mm)	0.9 nH
Chip aluminum electrolytic capacitor (47 μF, Size: 8.4 x 8.3 x 6.3 mm)	6.8 nH
Chip tantalum electrolytic capacitor (47 μF, Size: 5.8 x 4.6 x 3.2 mm)	3.4 nH

ESL, together with capacitance, determines the resonant point of the capacitor and the anti-resonant frequency range of parallel capacitors. In practical design, choose capacitors with low ESL whenever possible.

Selecting Capacitors for EMC Filtering

For RF design, ceramic capacitors, polyester film capacitors, and polystyrene film capacitors are all good choices.

For EMI filters, the dielectric material requirements are not high. Common loose dielectrics such as X7R, Y5V, and Z5U are good choices. Usually, the absolute capacitance value, temperature coefficient, and voltage coefficient are not important.

Different types and capacitance values have different filtering ranges. Figure 3-13 compares typical insertion loss.

Figure 3-13 | Insertion loss of capacitors with different capacitance values

For 0805 SMD ceramic capacitors, a 0.01UF capacitor has better high-frequency filtering characteristics than a 0.1UF capacitor. It is recommended that boards with an operating frequency above 50MHZ, such as most transmission and MUSA boards, use 0.01UF filter capacitors instead of the 0.1UF capacitors that are currently used in large quantities.

Design Recommendations for Decoupling and Bypass Capacitors

Select capacitors based on the self-resonance characteristics in the supplier's product data so that they meet the clock rate and noise frequency requirements of the design.
Add as many capacitors as possible within the required frequency range. For example, the 22nF capacitor shown in Figure 3-12 has a self-resonant frequency of nearly 11 MHz, and its useful impedance range (less than 1Ω) is 6MHz to 40MHz. Add as many capacitors as needed within that band to achieve the required decoupling level.
Place at least one decoupling capacitor as close as possible to each IC power pin to reduce parasitic impedance.
Place bypass capacitors and the IC on the same PCB plane whenever possible. Figure 3-14 gives an example. One point in Figure 3-14 requires special attention: in both layouts, the Vcc net has only one point connected to the Vcc plane. As a result, noise inside and outside the IC must travel through this single via to the power plane. The additional impedance of the via helps prevent noise from spreading to the rest of the system.

Figure 3-14 | Layout example
For multi-clock systems, split the power plane as shown in Figure 3-14. Use a capacitor with the correct value for each section. The power plane separated by slots isolates noise in one section from sensitive devices in other sections and also provides separation of capacitance values.
For systems whose clock frequency varies over a wide range, bypass capacitor selection is difficult. A better solution is to place two capacitors with values close to a 2:1 ratio in parallel. This provides a wider low-impedance region and a wider bypass frequency range. Figure 3-15 gives an example. The impedance peak still occurs, but it is less than 1.5Ω. The usable frequency range, where impedance is less than 1.5Ω, extends to nearly 3.25MHz to 100MHz. This multi-decoupling method is used only when a single IC requires a wide bypass frequency range and a single capacitor cannot cover that band. The capacitance values must remain within the 2:1 range to avoid the impedance peak exceeding the usable range.

Figure 3-15 | Decoupling capacitor design for multi-clock systems

The above applies to filtering at the signal end. It cannot be extrapolated to power decoupling capacitors.

Design of Bulk Capacitors

Bulk capacitors ensure that the supply voltage does not drop when the load changes quickly to its heaviest condition. Bulk capacitors fall into two types: board-level bulk capacitors and device-level bulk capacitors.

A. Board-level bulk capacitors: These ensure that the supply voltage at all locations on the board does not drop when the load changes quickly to its heaviest condition. On high-frequency, high-speed boards, and on backplanes where conditions allow, distribute a certain number of larger tantalum capacitors (1uf, 10uf, 22uf, 33uf) evenly to keep the same voltage value consistent across the board.

B. Device-level bulk capacitors: These ensure that the supply voltage around the device does not drop when the load changes quickly to its heaviest condition. For devices with higher operating frequency, speed, and power consumption, place 1 to 4 larger tantalum capacitors (1uf, 10uf, 22uf, 33uf) around the device to keep its operating voltage stable during fast changes.

The design of bulk capacitors should be distinguished from the design of decoupling capacitors. The following design suggestions apply:

When a board has multiple supply voltages, still use only one capacitance value for the bulk capacitors of each supply voltage. Generally, use surface-mount tantalum capacitors and select 10uf, 22uf, or 33uf as needed.
Chips with different supply voltages form a cluster. Distribute the bulk capacitors evenly within this cluster, as shown below.

Figure 14 | Distribution of energy storage capacitors