PCB EMC Design Guide: Stackup, Layout, Routing and Backplane Practice

Electromagnetic compatibility is decided long before the first EMC test is run. It is decided when the layer count is chosen, when the power and ground planes are assigned their positions in the stackup, when a clock module is placed on the board, when a decoupling capacitor is selected, and when a high-speed trace is allowed to cross a split in a reference plane. This guide treats EMC as a PCB design discipline rather than a compliance activity. It defines what EMC means in the formal, standards-based sense, explains why EMC work has to be pushed into the pre-research and development phases instead of being left to the test laboratory, and then sets out a complete working structure for doing the job at the board level.

The scope is deliberately broad because the failure modes are broad. The material moves from stackup and layer assignment, through module partitioning and special-device placement, through filtering components and capacitor behavior, through ground splitting and ground tying, into transmission-line modeling, reflection and crosstalk, preferred routing layers, impedance control and differential impedance trends, via modeling, slot and split-crossing handling, and the relationship between signal quality and EMC. It then extends to backplane EMC design, RF PCB EMC design, and a set of safety and construction topics that belong in the same reference. The intent is practical: give hardware engineers a set of reference positions from which they can weigh competing factors and complete the physical implementation of a schematic successfully, rather than a list of rules to be applied without judgment.

Highlights:

• EMC is defined by national military standard GJB72-85, clause 5.10, as the coexistence state in which equipment, subsystems and systems perform their respective functions in a shared electromagnetic environment without causing or suffering impermissible degradation.
• Layer count, stackup order and reference-plane assignment (sections 1.1.1, 1.3.1 and 1.3.2) fix the impedance of the power and ground planes and the electromagnetic environment between them before any routing decision is made.
• Differential impedance behavior is documented against differential pair spacing for dielectric thicknesses of 5 mil, 13 mil and 25 mil, giving designers a direct trade-off between stackup height and routing density.

Scope and Applicability

This technical guide was compiled against national standard GJB72-85, the standards of the former Ministry of Posts and Telecommunications, and the relevant international standard series. Its purpose is to consolidate and disseminate proven PCB EMC design practice, and at the same time to probe actively into areas where the answers are still uncertain. It is positioned as a PCB EMC design reference for hardware engineers. It is not a mandatory specification and it does not replace project-specific requirements. It is a body of experience that a designer can draw on, adapt, and use to reach a balanced decision when layout, cost, manufacturability and EMC pull in different directions.

Because the guide was assembled from working experience rather than from first principles alone, and because the EMC field still contains many unknowns, some of the viewpoints and recommendations it contains are summaries of what has worked in practice rather than derivations from theory. Readers are expected to treat the content critically, test it against their own products, and feed corrections and refinements back into the next revision.

The Formal Definition of EMC

National military standard GJB72-85, "Terms and definitions for electromagnetic interference and electromagnetic compatibility," clause 5.10, defines electromagnetic compatibility as the coexistence state in which equipment (subsystems, systems) can perform their respective functions together in a common electromagnetic environment. The definition has two halves, and both matter to a PCB designer. The first half states that the equipment will not suffer impermissible degradation caused by electromagnetic emissions from other equipment in the same environment. The second half states that the equipment will not cause impermissible degradation in other equipment in that same environment because of its own emissions.

This symmetry is the reason EMC cannot be reduced to a shielding or filtering checklist. A design that is immune but noisy is not compliant, and a design that is quiet but susceptible is not compliant either. Every layout decision that reduces emissions, such as shrinking a current loop or keeping a return path continuous, usually also improves immunity, and every decision that degrades a return path usually hurts both. The two halves of the definition should be evaluated together.

Why EMC Work Must Start in the Design Phase

Organizations that handle EMC well do not handle it at the end of the project. They invest heavily during pre-research and development and carry out EMC engineering work inside the design phase itself, so that potential compatibility problems are prevented rather than discovered. Prevention is cheap; remediation after a board is fabricated, assembled and tested is not. A stackup change, a plane reassignment, or a relocated clock circuit costs an afternoon during layout and costs a board spin afterwards.

Structured EMC work spans several disciplines that are normally organized separately: EMC working groups, EMC laboratories, CAD research groups, signal integrity research groups, electromechanical engineering groups, and the product lines themselves. Each contributes a different part of the picture. The laboratory supplies measurement and failure analysis, the signal integrity group supplies the transmission-line and impedance view, the CAD group supplies the layout rules and tooling, and the electromechanical group supplies enclosure, grounding and shielding constraints. The PCB sits at the intersection of all of them.

As the origin of EMI, device selection, schematic design and PCB design have progressively received the attention they deserve, and hardware developers now routinely place EMC requirements on PCB design rather than treating the layout as a purely mechanical translation of the netlist. This guide exists to support that expectation. It collects the design positions that have proven useful, and it deliberately includes open questions so that the reader does not mistake a working habit for a law of physics.

How This Guide Is Organized

The content is organized into five parts: layout, routing, backplane EMC design, RF PCB EMC design, and an appendix. The first two parts carry most of the general-purpose material and apply to almost any digital board. The third and fourth parts specialize that material for backplanes and for RF boards, where the same principles reappear with different constraints. The appendix collects safety and construction topics that a designer needs to be aware of because they change what can be placed where.

Part 1: Layout

Part 1 begins with layer setup, and the ordering is intentional. Section 1.1 covers a reasonable layer count. Section 1.1.1 addresses the number of Vcc and GND layers, and section 1.1.2 addresses the number of signal layers. Section 1.2 sets board performance targets against cost requirements, because the layer count is where EMC ambition and bill-of-materials reality meet. Section 1.3 then fixes the relative positions of the power layer, the ground layer and the signal layers. Section 1.3.1 examines the impedance of the Vcc and GND planes together with the EMC environment between power and ground. Section 1.3.2 treats Vcc and GND as reference planes and explains the roles they play and the differences between them. Section 1.3.3 settles the relative placement of power, ground and signal layers. A designer who works through this sequence ends up with a stackup that has a defensible reason for every layer.

Section 2 covers module partitioning and the placement of special devices. Partitioning can be done by function, by frequency, by signal type, or by a combination of all three, and section 2.1.4 discusses the combined approach. Section 2.2 addresses the devices that most often ruin an otherwise sound layout: the power supply section, the clock section, inductive coils, bus drivers, and filter components. Each of these has a preferred location and a preferred orientation, and each of them interacts with the planes beneath it.

Section 3 is devoted to filtering. After an overview, it examines the filter components themselves: resistors, inductors, capacitors, ferrite beads and common-mode chokes. Section 3.3 covers filter circuit topologies and the layout and routing of those circuits. Section 3.4 is the longest treatment and deals with capacitors in PCB EMC design: the different types of filter capacitor, the self-resonance problem, the effect of ESR on the amplitude-frequency characteristic of paralleled capacitors, the effect of ESL on the same characteristic, capacitor selection, design recommendations for decoupling and bypass capacitors, and the design of energy-storage capacitors.

Section 4 closes Part 1 with ground splitting and ground tying: what grounding means, what grounding is for, and the basic grounding methods. Single-point grounding and multi-point grounding are presented separately, followed by the mixed grounding arrangements that combine them, the general selection principles for grounding methods, and the application of those principles at system, backplane and single-board level.

Part 2: Routing

Part 2 starts with the transmission-line model, reflection and crosstalk, since nearly every routing rule in the rest of the guide is derived from them. Section 1.3.1 and section 1.3.2 introduce the two canonical geometries, microstrip and stripline. Section 1.4 covers reflection, and the crosstalk section follows.

Section 2 addresses the choice of routing layer. It compares surface routing with inner-layer routing for microstrip and for stripline, then compares the two geometries directly, and finally assigns a priority level to each routing layer so that the most sensitive nets get the best transmission environment and the least sensitive nets get what is left.

Section 3 is impedance control. It begins with the physical meaning of characteristic impedance, distinguishing input impedance from characteristic impedance and then extending the treatment to even-mode impedance, odd-mode impedance and differential impedance. Section 3.2 examines how the fabrication process affects impedance control, which is where simulation meets the real copper thickness, dielectric constant and etch profile. Section 3.3 deals with differential impedance control and documents how differential impedance varies with differential pair spacing at three dielectric thicknesses: 5 mil, 13 mil and 25 mil. These three cases give the designer a direct feel for how a taller stackup and a tighter spacing trade against each other. Section 3.4 covers the effect of shielding ground traces on impedance, both the effect of the spacing between the ground trace and the signal trace and the effect of the ground trace width. Section 3.5 works through an impedance control case.

Section 4 covers the handling of special signals, and section 5 addresses vias: the via model, the mathematical model of a via, the factors that influence that model, and the effect of vias on signal conduction and radiated emission, including the effect of vias on impedance control and the effect of via count on signal quality.

Section 6 is the split-plane and slot discussion. It explains how slots arise, both from power and ground plane splitting and from via arrays packed too densely. It then explains how a slot affects the EMC performance of the board, using the surface current distribution of high-speed and low-speed signals, the concept of split ground, and the specific problem of a signal crossing a slot in a power or ground plane. Section 6.3 lists the remedies: impedance-controlled high-speed traces must never cross a split; incompatible circuits on the same board must be given separate ground regions; when a crossing is unavoidable a bridge must be provided; connectors that face the outside world must not be placed over a gap in the ground plane; high-density connectors need their own treatment; and crossing a split in a quiet ground requires separate handling.

Section 7 ties signal quality and EMC together. It introduces both topics, identifies where they coincide, identifies where they diverge, and summarizes the relationship. The coincidence is useful because good signal integrity practice usually helps EMC. The divergence is important because there are cases where the two pull in opposite directions, and the designer needs to know which one to favor.

Part 3: Backplane EMC Design

The backplane part begins with slot arrangement. It covers the interconnection requirements between boards, board position structure, the influence of that structure, and the choice of interconnect levels and driver devices. It then addresses backplane EMC design itself: the signal arrangement and EMC design of connectors, connector selection, connector models and pin signal assignment, impedance matching, and power and ground distribution. The distribution section covers the effect of power splitting and hot swapping on the power supply, ground splitting and the connection of the various ground types, and shielding layers.

Part 4: RF PCB EMC Design

The RF part starts with materials, comparing ordinary laminate with RF-specific laminate. It then covers isolation and shielding: isolation, component placement, the separation of sensitive circuits from strongly radiating circuits, shielding materials and methods, and the dimensions of shielding cavities. RF PCB filtering is treated in its own section, covering the filtering of power and control lines and the filtering of frequency synthesizer data lines, clock lines and enable lines. Grounding follows, including grounding classification, large-area grounding, grouped local grounding, RF device grounding, the problems to watch for when grounding, and the distribution of ground planes. RF routing covers impedance control, corners, microstrip routing, microstrip couplers, microstrip power dividers, basic microstrip elements, stripline routing, and the practice of placing ground copper on both sides of an RF trace. The part closes with additional design considerations.

Part 5: Appendix

The appendix collects safety and construction material. It covers general criteria for safety markings, the hazards of electric shock and stored energy, fuses on PCBs, and replaceable batteries. It then addresses creepage distance and electrical clearance, and the coating of printed circuit boards, including board mechanical strength, the flammability rating of PCB material, thermal cycling and thermal aging tests, dielectric strength testing and scratch resistance testing. It closes with wiring and power supply considerations. These topics are not EMC theory, but they constrain where components can go, how far copper must be kept from an edge, and what insulation is acceptable, so they belong in the same reference.

How to Use This Reference

The material is arranged in the order in which design decisions are actually made. Stackup and partitioning come first because everything downstream depends on them. Filtering and grounding follow because they are the two most common remedies applied during layout. Routing and impedance control come next because they determine whether the layout survives contact with a fast edge. Backplane and RF specialization come last because they apply the same foundations under tighter constraints. A reader facing a specific problem can go directly to the relevant section; a reader building a design process from scratch should work through the parts in order.

Two cautions apply throughout. First, the recommendations in this guide are starting positions, not universal requirements. A stackup that works for a backplane with many dense connectors will not be the right stackup for a small RF module, and a grounding scheme that suits one product family may be inappropriate for another. Second, every rule here is a compression of physics that the reader can verify. When a rule and a measurement disagree, the measurement wins, and the rule should be revisited.

Questions about specific applications, and suggestions for improving this material, are welcome and should be directed to the group responsible for maintaining it, so that practical PCB EMC design problems can be worked through collectively and the next revision can be better than this one.

PCB EMC Design Guide

1 Purpose

This guide defines the requirements for electromagnetic compatibility (EMC) design on the company's PCBs. Its purpose is to take the EMC design requirements established at the circuit level and ensure that they are implemented in the PCB. The guide summarizes and promotes existing achievements in PCB EMC design. It also combines lessons learned during PCB design with EMC test data from products, so that hardware engineers can use the result as a practical reference when they perform PCB EMC design. EMC design on a PCB is not a separate activity that begins after the schematic is complete. It is a set of constraints that must be carried through stackup selection, placement, routing, and grounding. The guide therefore treats the PCB as part of the EMC control plan, not as a passive carrier of components. When the PCB structure is chosen correctly, it preserves the effectiveness of filters, transient suppressors, and shielded enclosures. When it is chosen incorrectly, it can create unintended antennas, common-mode paths, and ground loops that degrade the performance of an otherwise sound circuit. The guide is a living document and will be upgraded continuously. Readers should always use the latest version.

2 Scope

This guide applies to the EMC design of single boards and backplanes. These are the board types for which the company carries out PCB-level EMC design, and the guidance therefore addresses the layout, interconnection, and grounding decisions that are made on those boards. For a single board, the relevant decisions include plane assignment, decoupling placement, clock and interface routing, and the treatment of cables and connectors at the board boundary. For a backplane, the same principles apply, but the interconnect structure and the multiple board interfaces make return-path continuity and connector pin assignment especially important. The scope is limited to EMC design at the PCB level. The guide does not address enclosure design, cable assembly design, or system-level grounding, except where those topics directly affect the PCB.

3 Definitions

EMC: Electromagnetic Compatibility.

EMI: Electromagnetic Interference.

EMC is the ability of equipment to function in its electromagnetic environment without introducing intolerable disturbances to that environment. EMI is the degradation of performance caused by an electromagnetic disturbance. In design practice, EMC is the target and EMI is the failure mode. The terms are sometimes used interchangeably in informal discussion, but this guide keeps the distinction: EMC describes the desired condition, while EMI describes the unwanted coupling that must be prevented. These two definitions frame the technical sections that follow.

4 Referenced Standards and Resources

The following standards and reference materials are cited in this guide. The provisions of the standards listed below become part of this guide through reference. At the time of publication, the editions shown were valid. All standards are subject to revision, and parties using this guide should investigate the possibility of applying the latest editions of the standards listed below. The list combines textbooks, EMC training material, standards, and PCB design specifications. This mix reflects the guide's intent to connect EMC principles with practical PCB design rules. The standards are cited because their provisions become part of this guide; the other references provide background and supporting methods. Users should treat the list as a starting point for detailed study and should consult the cited documents when a design decision depends on a specific requirement.