PCB Layer Setup and Stackup Design: Layer Count, Power and Ground Planes

Layer setup is the first decision made in EMC-oriented PCB design, and it is also the decision with the longest-lasting consequences. The total layer count of a board is simply the sum of its power layers, ground layers and signal layers, but the number itself matters far less than how those layers relate to one another. The relative positions of power, ground and signal planes, together with the way power and ground planes are split, determine the EMC performance of the finished assembly. Once the stackup is frozen and the bare board is fabricated, the EMC environment of the design is essentially locked in; routing rules can only work within the framework that the stackup provides.

This first part of the series explains how to arrive at a layer count that fits a given product. It covers how power and ground layer counts are derived from supply rails and reference requirements, how signal layer count is judged from placement and routing density together with board-level operating frequency, how performance targets are balanced against cost, and why the relative placement of power, ground and signal layers deserves attention before any routing begins.

Highlights:

Layer count is a systems decision driven by supply diversity, signal density, operating frequency and the number of signals needing special routing, not by habit or by the smallest number a fabricator will accept.
For boards facing strict EMC limits such as CISPR16 CLASS B certification, adding ground planes where the cost can be absorbed is one of the most effective levers available in PCB EMC design.
Every power plane needs its own adjacent reference plane, and placing the main power plane as close as possible to its return plane lowers power-plane impedance through plane-to-plane coupling capacitance.

Layer Setup

In EMC design of a PCB, layer setup is the item tackled first, because everything downstream depends on it. The layer count of a board is composed of the number of power layers, the number of ground layers and the number of signal layers. The relative positions of power, ground and signal layers, and the splitting of power and ground planes, are decisive for the EMC indicators of the board.

Determining a Reasonable Layer Count

The layer count is determined jointly by the types of power and ground nets on the board, the signal density, the board-level operating frequency, the number of signals with special routing requirements, and the overall performance target weighed against what the program can afford to spend. For products with severe EMC requirements, for example a product that must pass CISPR16 CLASS B certification, and where the cost can be absorbed, adding ground planes is one of the decisive measures in PCB EMC design.

Power and Ground Layer Counts

The number of power layers is governed by how many supply rails the board carries. For a PCB fed by a single supply, one power plane is enough. For multiple supplies that do not interleave with one another, a split power plane can be considered, provided that critical signal routing on adjacent layers does not cross the split regions. For boards whose supplies do interleave with one another, and this applies especially to ICs such as the 8260 that are fed by several supplies occupying interleaved areas, two or more power planes must be considered. Each power plane must satisfy the following conditions:

It carries either a single supply, or several supplies that do not interleave.
Critical signals on adjacent layers do not cross the split regions.

In addition to meeting the same conditions as the power planes, the number of ground layers must also account for the following:

There is a relatively complete ground plane beneath the component side, that is, layer 2 or the second layer from the bottom.
Critical signals, including high-frequency, high-speed and clock nets, each have an adjacent ground plane.
Critical power rails have a corresponding adjacent ground plane, for example 48V placed next to BGND.

Signal Layer Count

With current CAD tools, once the netlist has been imported the EDA software can produce a placement and routing density parameter report, and this report gives a rough indication of how many signal layers the design will need. An experienced CAD engineer then combines those parameters with the board-level operating frequency, the number of signals with special routing requirements, the performance target of the board and the cost that can be accepted, and finally settles the signal layer count.

Signal layer count is driven primarily by functional realization. From an EMC standpoint, what has to be considered is the shielding or isolation provided for critical signal nets, meaning the strongly radiating nets on one hand and the small, weak signals that are easily disturbed on the other.

Performance Targets versus Cost Requirements

Competition in communications equipment puts relentless pressure on product development. Time, quality and cost are the basic conditions for beating competitors and, in many cases, for surviving. For high-end products, a moderate cost increase is unavoidable if a product of solid quality is to reach the market quickly. For mature products, or for products under heavy price pressure, layer count has to be minimized and processing difficulty reduced, so that a product with an appropriate price-performance ratio can enter the market. Consumer products such as televisions, VCD players and computer motherboards generally use boards of six layers or fewer, and they deliberately give up some performance margin in order to meet high-volume production requirements and comply strictly with the relevant process specifications. For high-end communication equipment, however, over-emphasizing cost and process factors in the early stage of development will inevitably affect both development schedule and product quality.

The table below gives the PCB processing price ratios agreed with PCB suppliers. For confidentiality, only a price ratio per square centimeter is given, indexed to the 4-layer sample with a board thickness of 2.0mm, which serves as the reference value of 1.

Layer count	Sample		Volume production
Layer count	Board thickness 2.0mm	Board thickness 3.0mm	Board thickness 2.0mm	Board thickness 3.0mm
2	0.47	0.59	0.32	0.34
4	1 (reference)	1.26	0.59	0.62
6	1.41	1.76	0.82	1.03
8	2.03	2.47	1.29	1.53
10	3.35	3.97	1.62	1.62
12	4.56	5.59	2.15	2.21
14	6.47	7.65
16	9.12	10.59

Relative Placement of Power, Ground and Signal Layers

Once the layer count is settled, the next question is where the power, ground and signal layers sit with respect to one another. The placement directly affects the impedance seen by the power delivery network and the coupling path between power and ground.

Impedance of Vcc and GND Planes and the Power-Ground EMC Environment

This topic deserves deeper investigation. The following points summarize current understanding and are given for reference.

Power and ground planes each have their own characteristic impedance, and the impedance of a power plane is higher than that of a ground plane.
To reduce the impedance of the power plane, place the main power plane of the PCB adjacent to its corresponding ground plane and keep the two as close together as possible, so that the coupling capacitance between them lowers the power plane impedance.
The plane capacitance formed by the power and ground planes, together with the decoupling capacitors on the board, produces a power-ground capacitance with a fairly complex frequency response. Its effective decoupling bandwidth is relatively wide, but resonance problems exist.

Vcc and GND as Reference Planes: Roles and Differences

Both power and ground planes can serve as reference planes, and each provides some shielding. Relatively speaking, however, a power plane has higher characteristic impedance and a larger potential difference from the reference level. From a shielding standpoint, the ground plane is generally connected to ground and used as the zero-level reference point, so its shielding effectiveness is far better than that of a power plane.

When selecting a reference plane, the ground plane should be preferred.

Once the numbers of power, ground, and signal layers are fixed, their relative arrangement is a topic that every EMC engineer must address.

General principles for board stackup are:

Place a ground plane directly below the component side (layer 2) to provide device shielding and a reference plane for top-layer routing.
Keep every signal layer adjacent to a ground plane whenever possible.
Avoid placing two signal layers directly adjacent to each other.
Place the main power plane adjacent to its corresponding ground plane whenever possible.
Maintain symmetry of the lamination structure.

For motherboard stackups, long parallel routes are difficult to control on existing motherboards. For board-level operating frequencies above 50 MHz, the following stackup principles are recommended; for frequencies below 50 MHz, they can be used as a reference and relaxed as appropriate:

Use complete ground planes on the component side and solder side for shielding.
Do not place parallel routing on adjacent layers.
Keep every signal layer adjacent to a ground plane whenever possible.
Route critical signals adjacent to a ground plane and do not let them cross splits.

Note: When setting up layers for a specific PCB, apply these principles flexibly. Once the principles are understood, determine the stackup from the actual board requirements, such as whether a dedicated critical-routing layer is needed and how the power and ground planes will be split. Do not copy them mechanically or fixate on a single rule. Owing to space limits, only general principles are listed here for reference.

The following sections discuss specific board stackups.

For a four-layer board, Option 1 is preferred and Option 3 is acceptable.

Option	Power layers	Ground layers	Signal layers	Layer 1	Layer 2	Layer 3	Layer 4
1	1	1	2	S	G	P	S
2	1	1	2	G	S	S	P
3	1	1	2	S	P	G	S

Option 1

This option is the primary stackup used for current four-layer PCBs in the CAD group. A ground plane is placed below the component side, and critical signals are preferably routed on the top layer. For layer thickness, the following is recommended:

Meet impedance-control requirements.
Do not make the core between GND and POWER too thick, so as to reduce the distributed impedance of the power and ground planes and ensure the decoupling effect of the power plane.

To achieve a certain shielding effect, some designers try to place the power and ground planes on the top and bottom layers, which is Option 2:

Option 2

This option has at least the following drawbacks even though it aims at the desired shielding effect:

Power and ground are too far apart, so the power-plane impedance is relatively high.
The power and ground planes are highly incomplete because of component pads and similar features.
Because the reference planes are incomplete, signal impedance is discontinuous.

In practice, because SMT devices are widely used and component density continues to increase, the power and ground planes in this option can hardly serve as complete reference planes, and the expected shielding effect is difficult to achieve. Option 2 therefore has limited application. For certain individual boards, however, Option 2 can be the best stackup. The following is a case in which Option 2 was used on an interface filter board for a specific product.

Case (special example): During the design of an interface filter board for a product, the following conditions arose: A. The board has no power plane; only GND and PGND, each occupying one plane. B. Routing on the board is simple, but because it is an interface filter board, radiation from the routing must be considered. C. The board has few SMT components; most are through-hole.

Analysis: 1. Because the board has no power plane, the power-plane impedance issue does not exist. 2. Because there are few SMT components and placement is single-sided, if the surface layers are used as planes and routing is placed on inner layers, reference-plane integrity is largely ensured, and the second layer can be copper-poured to provide a reference for the small amount of top-layer routing. 3. As an interface filter board, radiation from PCB routing must be considered; if inner layers are used for routing and the surface layers are GND and PGND, the routing is well shielded and transmission-line radiation is controlled.

For these reasons, Option 2 was selected for this board: GND, S1, S2, PGND. Because a small number of short routes remained on the top layer and the bottom layer was a complete ground plane, copper was poured on the S1 routing layer to provide a reference for the top-layer routing.

In five interface filter boards for the same product, the designers reached the same conclusion and chose Option 2, which is likewise a classic stackup.

These special cases are listed to make the point that the principles of layer arrangement must be understood rather than copied mechanically.

Option 3

This option is similar to Option 1 and is suitable when most components are placed on the bottom side or critical signals are routed on the bottom layer. In general, its use is restricted.

For a six-layer board, Option 3 is preferred, Option 1 is acceptable, and Options 2 and 4 are backups.

Six-Layer Stackup Scheme Comparison

The table compares four six-layer stackup options. The columns list the number of power planes, ground planes, and signal layers, followed by the layer sequence from layer 1 through layer 6. In the layer columns, S denotes a signal layer, P denotes a power plane, and G denotes a ground plane. Scheme 1 and Scheme 2 each use one power plane, one ground plane, and four signal layers. Scheme 3 and Scheme 4 each use one power plane, two ground planes, and three signal layers.

Scheme	Power Planes	Ground Planes	Signal Layers	Layer 1	Layer 2	Layer 3	Layer 4	Layer 5	Layer 6
1	1	1	4	S1	G	S2	S3	P	S4
2	1	1	4	S1	S2	G	P	S3	S4
3	1	2	3	S1	G1	S2	P	G2	S3
4	1	2	3	S1	G1	S2	G2	P	S3

For a six-layer board, Scheme 3 is the first choice. Its preferred routing layer is S2, followed by S3 and S1. The main power plane and its corresponding ground plane are placed on layers 4 and 5. When the layer thicknesses are set, the spacing between S2 and P should be increased, and the spacing between P and G2 should be reduced. The spacing between G1 and S2 is reduced accordingly. This arrangement lowers the impedance of the power plane and reduces the influence of the power plane on S2.

Scheme 1 is ordered S1, G, S2, S3, P, S4. The ground plane is on layer 2, between S1 and S2, and the power plane is on layer 5, between S3 and S4. Scheme 2 is ordered S1, S2, G, P, S3, S4. In Scheme 2, the ground and power planes are adjacent on layers 3 and 4, in the center of the stackup, while S1 and S2 are above them and S3 and S4 are below them.

When cost constraints are tighter, Scheme 1 can be used. Its preferred routing layers are S1 and S2, followed by S3 and S4. Compared with Scheme 1, Scheme 2 keeps the power and ground planes adjacent, which reduces power impedance. However, in Scheme 2, S1, S2, S3, and S4 are all exposed on the outside, and only S2 has a good reference plane.

Scheme 3 is ordered S1, G1, S2, P, G2, S3. In this stackup, S1 is adjacent to G1, S2 lies between G1 and P, and S3 is adjacent to G2. Scheme 4 is ordered S1, G1, S2, G2, P, S3. Here S2 lies between G1 and G2. For cases with a small number of local signals that have high requirements, Scheme 4 is more suitable than Scheme 3 because it provides an excellent routing layer, S2.

Eight-Layer Board: Preferred Options 2 and 3, Option 1 Acceptable

In the stackup table, S denotes a signal layer, G denotes a ground plane, and P denotes a power plane. The layer numbers run from the top of the board to the bottom. The Power, Ground, and Signal columns give the number of layers assigned to each function, so the signal count also indicates the number of routing layers available. The table compares five eight-layer arrangements.

Scheme	Power	Ground	Signal	1	2	3	4	5	6	7	8
1	1	2	5	S1	G1	S2	S3	P	S4	G2	S5
2	1	3	4	S1	G1	S2	G2	P	S3	G3	S4
3	2	2	4	S1	G1	S2	P1	G2	S3	P2	S4
4	2	2	4	S1	G1	S2	P1	P2	S3	G3	S4
5	2	2	4	S1	G1	P1	S2	S3	G2	P2	S4

Option 1 is the acceptable baseline. It provides five signal layers, the largest routing capacity among the five arrangements, with two ground planes and one power plane. Its limitation is the S2 and S3 pair: those two signal layers are directly adjacent, and the power plane at L5 has no adjacent ground plane. Option 1 is therefore suitable when routing density is the primary constraint and the coupling between S2 and S3 can be tolerated. When the design can give up one routing layer, Option 2 provides a stronger reference-plane arrangement.

For a single power supply, Option 2 reduces adjacent signal-layer pairs compared with Option 1. Option 1 has five signal layers and two ground planes. Its S2 and S3 layers are adjacent, and the power plane at L5 is not next to a ground plane. Option 2 changes the assignment to four signal layers and three ground planes. It places the main power plane next to G2 and ensures that every signal layer is adjacent to a ground plane. S1 references G1, S2 references G1 and G2, S3 references G2 and G3, and S4 references G3. The cost is one routing layer: the fifth signal layer in Option 1 becomes a third ground layer in Option 2. For a single-supply design that values return-path continuity and isolation over raw routing capacity, Option 2 is the better choice.

For a dual power supply, Option 3 is recommended. It combines no adjacent routing layers, a symmetrical lamination structure, and adjacency between the main power plane and ground. The layer sequence is S1, G1, S2, P1, G2, S3, P2, S4. There is no signal layer directly next to another signal layer. P1 is next to G2, so the main power plane has a nearby ground reference. S4 references P2 rather than a ground plane, so it should carry fewer critical traces. Keeping sensitive or high-speed routing away from S4 limits the risk associated with that reference arrangement. Option 3 therefore fits boards that need two power planes and can accept reduced critical-routing capacity on the bottom signal layer.

Option 4 also has no adjacent routing layers and a symmetrical lamination structure, but its power-plane impedance is relatively high. P1 and P2 occupy L4 and L5, while ground planes are placed at L2 and L7 and signal layers at L1, L3, L6, and L8. Because the power planes are adjacent to each other rather than directly to ground, the power-plane impedance is higher. To address this, the spacing between layers 3 and 4 and between layers 5 and 6 should be increased appropriately, while the spacing between layers 2 and 3 and between layers 6 and 7 should be reduced. These spacing changes are part of the stackup definition and should be reflected in the dielectric thicknesses. Option 4 is usable when the layer assignment is otherwise suitable and the power-plane impedance can be managed through controlled dielectric spacing.

Option 5 differs from Option 4 by ensuring that power and ground planes are adjacent. G1 is next to P1, and G2 is next to P2. This improves the power and ground plane pairing relative to Option 4. The cost is that S2 and S3 are adjacent, and S4 uses P2 as its reference plane. The adjacent S2 and S3 layers can couple, so routing on those layers must be controlled. S4, referenced to P2, is also less attractive for critical nets. Option 5 can be considered when the bottom layer has few critical traces and when crosstalk between S2 and S3 can be controlled. It is a conditional choice, not a default recommendation.

Ten-Layer Board: Recommended Options 2 and 3, Options 1 and 4 Acceptable

Ten-Layer Board: Four Stackup Configurations

The table below summarizes four candidate layer assignments for a ten-layer board. The columns numbered 1 through 10 correspond to the physical layers, counted from the top of the board downward. Inside the cells, S denotes a signal layer, G a ground layer, and P a power layer. The three leftmost data columns give the layer budget of each configuration: the number of power layers, ground layers, and signal layers it provides.

Scheme	Power	Ground	Signal	1	2	3	4	5	6	7	8	9	10
1	1	3	6	S1	G1	S2	S3	G2	P	S4	S5	G3	S6
2	1	4	5	S1	G1	S2	G2	S3	G3	P	S4	G4	S5
3	2	3	5	S1	G1	S2	P1	S3	G2	P2	S4	G3	S5
4	2	4	4	S1	G1	S2	G3	P1	P2	G3	S3	G4	S4

All four configurations share the same outer architecture: a signal layer on layer 1 backed by a ground plane on layer 2, and a signal layer on layer 10 backed by a ground plane on layer 9. The differences are concentrated in the middle of the stack, where the plane pairs and the inner routing layers are arranged. This is why the choice between the schemes depends on the number of supplies and on how much high-speed routing must be accommodated, rather than on the behaviour of the outer layers.

Reading the four configurations side by side makes the trade-offs explicit. Scheme 1 spends the least on planes, with one power layer and three ground layers, and therefore releases six layers for routing, but its signal layers pile up in adjacent pairs. Scheme 2 raises the ground count to four and keeps every signal layer directly adjacent to a ground plane, at the cost of one routing layer. Schemes 3 and 4 both split the supply into two planes, P1 and P2, which is why their signal counts fall to five and four respectively.

Scheme 3: Balanced Performance and Cost

In this configuration the spacing between layers 3 and 4, and between layers 7 and 8, is widened, while the spacing between layers 5 and 6 is reduced. The main power plane and its corresponding ground plane should be placed on layers 6 and 7. Widening the gaps beside a routing layer reduces the coupling between neighbouring signal layers, whereas tightening the 5-6 gap increases the capacitance formed by the power and ground pair. Preferred routing layers are S2, S3, and S4, followed by S1 and S5. The scheme suits boards whose signals do not differ greatly in their routing requirements, and it balances performance against cost, which makes it the recommended option for most designs. One precaution applies: avoid long parallel runs between S2 and S3.

Scheme 4: Excellent EMC at the Cost of One Routing Layer

Scheme 4 delivers excellent EMC performance, but compared with Scheme 3 it gives up one routing layer. It is the recommended choice for critical boards where cost pressure is low, EMC targets are demanding, and two power planes are mandatory. Preferred routing layers are S2 and S3.

Single Power Plane: Scheme 2 First, Scheme 1 Second

When the stackup can carry only one power plane, Scheme 2 should be considered first and Scheme 1 second. Scheme 1 has an obvious cost advantage because it converts a ground layer into a routing layer, but it places too many routing layers directly next to one another, so long parallel traces are difficult to control. In practical terms, the adjacent signal pairs in the middle of that stack allow crosstalk and unwanted coupling to build up over the length of the run. Scheme 2 removes that weakness by keeping every signal layer referenced to a ground plane, and the single routing layer it costs is usually a fair exchange.

Twelve-Layer Boards

For a twelve-layer board, Schemes 2 and 3 are recommended, Schemes 1 and 4 remain usable, and Scheme 5 is kept as a backup option.

12-Layer Stackup Scheme Comparison

The five candidate arrangements below all use the same 12-layer numbering. In the table, S denotes a signal layer, G a ground plane and P a power plane. The Power, Ground and Signal columns give the number of layers of each type, while the numbered columns 1 through 12 describe the sequence from the top layer to the bottom layer. Signal layers are labeled S1, S2 and so on in the order in which they appear, so the table shows at a glance how many routing layers each option actually provides and how the reference planes are distributed around them.

Scheme	Power	Ground	Signal	1	2	3	4	5	6	7	8	9	10	11	12
1	1	4	7	S1	G1	S2	G2	S3	P	S4	G3	S5	S6	G4	S7
2	1	5	6	S1	G1	S2	G2	S3	G3	P	S4	G4	S5	G5	S6
3	2	4	6	S1	G1	S2	G2	S3	P1	G3	S4	P2	S5	G4	S6
4	2	5	5	S1	G1	S2	G2	S3	G3	P1	P2	G4	S4	G5	S5
5	2	3	7	S1	G1	S2	S3	P1	G2	S4	S5	P2	S6	G3	S7

Scheme 1 devotes a single layer to power and four to ground, which frees seven layers for routing. The top and bottom layers are signal layers (S1 and S7), ground planes occupy layers 2, 4, 8 and 11, and the only power plane sits at layer 6 between S3 and S4. The routing capacity here is the highest of the five options, but the distribution of reference planes is uneven: layers 9 and 10 are two signal layers placed directly against each other, with no ground or power plane between them, so any sensitive net routed on one of those layers has no adjacent reference plane to control its return path.

Scheme 2 reduces the routing count to six layers, with five ground planes and one power plane. Ground appears at layers 2, 4, 6, 9 and 11, and the power plane at layer 7 lies immediately below ground plane G3, forming a tightly coupled power-ground pair in the center of the board. Each of the six signal layers is adjacent to at least one ground plane, and no two signal layers are stacked together, so every routing layer has a continuous reference plane directly beside it.

Scheme 3 uses two power planes and four ground planes, leaving six signal layers. P1 at layer 6 is backed by G3 at layer 7, while P2 at layer 9 is bounded by ground plane G4 at layer 11 through signal layer S5. This arrangement supports two separate supply voltages without giving up too much routing area, but the second power plane is separated from the nearest ground plane by a signal layer.

Scheme 4 keeps five signal layers for routing and assigns two layers to power and five to ground. The two power planes P1 and P2 are placed adjacent to each other at layers 7 and 8, with ground planes G3 and G4 immediately above and below the pair, so the power distribution region is surrounded by ground on both sides. Signal layers occupy layers 1, 3, 5, 10 and 12, and each one is adjacent to a ground plane.

Scheme 5 is the most routing-intensive of the two-power-plane options, with seven signal layers and only three ground planes. Ground is present at layers 2, 6 and 11, and the two power planes sit at layers 5 and 9. The stack contains two pairs of adjacent signal layers, S2/S3 at layers 3 and 4 and S4/S5 at layers 7 and 8, which increases routing capacity but weakens the reference plane environment for high-speed nets.

Among these options, schemes 2 and 4 deliver excellent EMC performance, while schemes 1 and 3 offer a better cost-performance balance. The distinction follows directly from the layer counts: schemes 2 and 4 increase the number of ground planes and keep the power planes coupled to ground, which tightens the return path and reduces the loop area seen by high-speed signals. Schemes 1 and 3 trade some of that margin for additional routing layers or additional voltage planes, which lowers the layer count and the cost.

For boards with 14 layers or more, the number of possible combinations is too large to list individually. The same stacking principles should be applied and the actual arrangement analyzed case by case, using the same rules for signal-to-reference adjacency, power-ground pairing and symmetry about the board center.

The stackups above are general principles offered for reference. In a specific design, the arrangement should be adapted to the required number of power layers, the required number of routing layers, the quantity and proportion of nets that need special routing, and the way power and ground are split. Where a particular point remains open to debate, the relevant experimental data and design cases should be used to settle it; until such evidence is available, the recommended schemes should be given priority.

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